Harmonic Elimination and Reactive Power Compensation with a Novel Control Algorithm based Active Power Filter

Abstract

This paper presents a power system harmonic elimination using the mixed adaptive linear neural network and variable step-size leaky least mean square (ADALINE-VSSLLMS) control algorithm based active power filter (APF). The weight vector of ADALINE along with the variable step-size parameter and leakage coefficient of the VSSLLMS algorithm are automatically adjusted to eliminate harmonics from the distorted load current. For all iteration, the VSSLLMS algorithm selects a new rate of convergence for searching and runs the computations. The adopted shunt-hybrid APF (SHAPF) consists of an APF and a series of 7^th tuned passive filter connected to each phase. The performance of the proposed ADALINE-VSSLLMS control algorithm employed for SHAPF is analyzed through a simulation in a MATLAB/Simulink environment. Experimental results of a real-time prototype validate the efficacy of the proposed control algorithm.

I. INTRODUCTION

Current harmonics have become a major issue in distribution network because of the wide power electronic device applications in the industry. To overcome the current harmonic related problems, passive filters are connected in different configurations that represent a low cost solution [1], [2]. However, this mechanism has few drawbacks, such as resonance, size, instability, and inability to compensate for the changing harmonic current contents, which deject their implementation. To resolve these issues, an active filtering approach called active power filter (APF) was introduced as an advanced technique for harmonics elimination and reactive power compensation [3]-[7]. Nonetheless, the main disadvantage in using this approach is that the cost of power electronic inverters is high, especially for high power ratings. Morever, APF is difficult to implement in high-voltage applications. Another harmonic mitigation solution called shunt-hybrid APF (SHAPF) topology was investigated and introduced [8]-[10]. SHAPF is formed by the connection of an APF with one or more passive filters in a series. This type of configuration significantly reduces the rating. Passive filters absorb the harmonics injected by the nonlinear load and suppress the switching ripples generated from APF, which in turn enhances the filtering performance of the passive filter.

The generation of references in the form of voltage or current is the essential aspect of active filter control. The control strategies in frequency-domain include the fast Fourier method [11], the Kalman filter [12], and the wavelet transform. The frequency-domain approach requires large memory, slow response, and additional computational power. Moreover, this method may provide imprecise results during transient conditions. Time-domain approaches, such as d-q and p-q transformations, are based on the measurements and transformation of three-phase quantities [7]-[10]. However, these three- to two-phase transformations fail to work properly under unbalanced conditions [3], [13]. A recent study proposed a fast adaptive linear neural network (ADALINE) based time-domain approach for extracting the fundamentals from the distorted current [3]-[6]. The weights of ADALINE are generally updated using the least mean square (LMS) recursive algorithm [14]-[16].

This algorithm is commonly used in signal processing and control system application because of its simplicity and robustness. The rate of convergence of LMS algorithm directly depends on the fixed step-size parameter [17]. During steady state operations, a large step-size leads to a large offset and fast convergence rate, whereas a small step-size results in a slow convergence rate and small offset. These drawbacks can be addressed by implementing a time varying step-size. In the variable step-size LMS (VSSLMS) algorithm, step-size is dynamically adjusted during convergence [17], [18].

The eigenvalue decomposition of the autocorrelation matrix sometimes produces a zero eigenvalue, which causes the LMS adaptive filter to have undamped modes. These modes make the system unstable and should therefore be pushed to zero. In this event, a leakage factor is introduced in the autocorrelation matrix [19]-[21]. Implementing a leaky adjustment technique makes the convergence rate faster than the conventional LMS algorithm in case of a high input eigenvalue spread.

In this study, a new design of SHAPF that employs mixed ADALINE-VSSLLMS algorithm is proposed. Three ADALINEs in each phase are used to extract the harmonics and reactive components from the sensed load currents. A pulse width modulation control technique is used to generate gating pulses for the insulated gate bipolar transistors (IGBTs). Extensive simulations are conducted to emphasize the efficacy of the investigative results and the admirable performance of the proposed ADALINE-VSSLLMS control algorithm. Finally, the results are verified by implementing the proposed control algorithm in real-time using a SPARTAN-3A DSP processor.

The rest of the paper is organized into six sections. Following the Introduction, Section II describes the complete structure of SHAPF. Section III presents the mathematical equations of the proposed control algorithm. Section IV discusses the simulation results of SHAPF under different load conditions. Section V explains the development of a laboratory prototype model and the corresponding experimental results. Finally, Section VI describes the conclusion of the study.

 

II. SYSTEM DESCRIPTION

Fig. 1 shows the configuration of SHAPF. The low-rated APF and 7th tuned passive filters are connected directly to the AC-mains without using a coupling transformer. The 7th tuned passive filter provides a lower impedance path for the 11th and 13th harmonic frequencies as compared to 5th tuned passive filter, thereby resulting in a satisfactory filtering performance. Moreover, designing the 5th tuned passive filter is heavy, bulky, and expensive than the 7th tuned because of its large capacitance Cp value.

Fig. 1.Structure of the three-phase SHAPF.

APF is a three-phase voltage source inverter consisting of six switches and a DC-link capacitor (Cdc). A PI controller is employed to charge the DC-link capacitor to the desired voltage level. The nonlinear load comprises a diode bridge rectifier followed by a capacitor with an inductive load (RL, LL). The SHAPF, which employs the proposed control technique, is designed to detect its harmonics and reactive components and inject a filter current identical with the load harmonic current. The three-phase source voltages measured at the point of common coupling are (va, vb, and vc). The three-phase source currents, three-phase load currents, and three-phase SHAPF currents are denoted as (isa, isb and isc), (iLa, iLb and iLc), and (ifa, ifb and ifc), respectively.

 

III. MIXED ADALINE-VSSLLMS BASED HARMONIC AND REACTIVE COMPONENT ELIMINATION

The load current iLa(t), including the harmonics, can be described using a Fourier series as follows:

where iDC,a(t) is the fundamental or DC current component, and iAC,a(t) is the sum of all harmonics or AC current components of the load current. If the reactive component is simultaneously compensated by APF, then iDC,a(t) can be further divided into two terms shown below.

where ixa(t) and iya(t) are the active and reactive components of the fundamental load current, respectively. Combining Eqs. (1) and (2) yields the following expression:

The compensating current component ifa(t) can be derived as

where W = [w1a, w2a] is the weight vector of ADALINE.

Fig. 2 shows the block diagram of the ADALINE-VSSLLMS control algorithm for reference signal generation. This algorithm is composed of two neurons whose weights w1a(n) and w2a(n) are updated online by the VSSLLMS algorithm. The input of each neuron is fed by the sinusoidal x1a(n) and cosine x2a(n) reference inputs collected from the source voltage va(n) by the phase locked loop circuit. The difference between the primary nonlinear load current iLa(n) and the estimated components ira(n) induces an error signal ea(n). The weights of ADALINE are updated based on the VSSLLMS algorithm [19]-[21].

where Δ(n) is the variable step-size parameter, and γ(k) is the variable leakage factor. When γ(k) = 0, it behaves as a conventional LMS algorithm. The leakage factor is set to be large enough at the transient state to expedite the rate of convergence, but is reduced at the steady state. The variable step-size can be calculated as [17], [18]

where α and γ are constant values controlling the convergence time, and R(n) is the autocorrelation of ea(n) and ea(n - 1). This autocorrelation can be expressed as follows:

where β is an exponential weighting parameter. The variable leakage factor γ(k) can be adjusted with the below equations.

Fig. 2.Block diagram of ADALINE-VSSLLMS based reference signal generation in phase-a.

ADALINE-VSSLLMS aims to minimize the error and determine an optimal weight vector. Hence, ira(n) approximates ixa(n). The residual error can be obtained as

The cost function J(n) is defined as follows:

where E{.} is the statistical expectation operator, and ifa(n) is uncorrelated with ixa(n) and ira(n) because of the orthogonality of trigonometric functions. When ixa(n) = ira(n), the following expression is obtained:

The preceding equation is the best mean square estimation of ixa(n). When this condition is achieved, the references are estimated successfully [4].

 

IV. SIMULATION STUDIES

The newly developed ADALINE-VSSLLMS control algorithm for harmonics elimination is designed, modeled, and simulated in a MATLAB/Simulink environment. The device parameters employed in the simulation studies are given in the Appendix, and the initial parameters are Δ = 0.001, γ = 0.01, and W = 0.018.

The steady state response of SHAPF is presented in Fig. 3. The source voltage va, sinusoidal source current isa, nonlinear load current iLa , SHAPF current ifa, reference voltage vrefa, output of inverter voltage va′, DC-link capacitor voltage vdc, and reference current I0 are depicted in Figs. 3(a) to (h), respectively. These figures illustrate that the source waveforms are of pure sinusoids and are in phase. The voltage across the capacitor is well balanced with an average value of 130 V. The maximum and minimum values of vdc are 127 and 132 V, respectively. The magnitude of the reference current i0 is zero.

Fig. 3.Steady state waveforms of SHAPF; (a) source voltage va, (b) source current isa, (c) load current iLa, (d) SHAPF current ifa, (e) reference voltage vrefa, (f) output of inverter voltage va′, (g) DC-link capacitor voltage vdc, and (h) DC-current I0.

Figs. 4(a) to (h) depict the dynamic response when a sudden step change of load occurs. The load resistance changes from 32 Ω to 16 Ω and from 16 Ω to 32 Ω at 0.25 and 0.35 S, respectively. The Fig. 4 evidently demonstrates that isa and vdc exhibit a fast transient response, achieving a stable operation using the ADALINE-VSSLLMS control algorithm.

Fig. 4.Dynamic response under sudden load variations; (a) source voltage va, (b) source current isa, (c) load current iLa, (d) SHAPF current ifa, (e) reference voltage vrefa , (f) output of inverter voltage va′, (g) DC-link capacitor voltage vdc, and (h) DC-current I0.

Figs. 5(a) to (h) show the dynamic response of SHAPF, which adopts the proposed controller, under on- and off-load switching conditions. A three-level variation is conducted on iLa (100% to 0%, steady at 0%, 0% to 100%). The SHAPF exhibits a fast response of one-time period to settle down to a new value. When iLa is set to zero, isa takes 0.016 S to maintain the equal ifa. The DC-link capacitor charges to an over-shoot voltage of 140 V (7.69%) and to an under-shoot voltage of 125 V (3.84%) at the on- and off-load conditions, respectively.

Fig. 5.Dynamic response under on- and off-load switching conditions; (a) source voltage va, (b) source current isa, (c) load current iLa, (d) SHAPF current ifa, (e) reference voltage vrefa, (f) output of inverter voltage va′ , (g) DC-link capacitor voltage vdc, and (h) DC-current I0.

Fig. 6 demonstrates the active and reactive powers on the load and source sides of the distorted power system. With SHAPF, the instantaneous active power is 1.48×104 W, and the reactive power is zero. The simulated waveforms of the system power factor are depicted in Fig. 7. The power factor is upgraded from 0.81 to 0.98 when SHAPF is connected.

Fig. 6.Simulated waveforms; (a) instantaneous active power PL on load side, (b) instantaneous reactive power QL on load side, (c) instantaneous active power PS on source side, and (d) instantaneous reactive power QS on source side.

Fig. 7.Simulated waveforms of the system power factor; (a) before compensation, (b) after compensation.

The harmonic distortions of iLa and isa with the application of SHAPF are depicted in Figs. 8(a) to (b), respectively. During the steady state operation, the harmonic levels of iLa and isa are 2.64% and 40.98%, respectively. These values are well below the restrictions imposed by the IEEE standard 519-1992.

Fig. 8.Total harmonic distortion; (a) load current, (b) source current.

Table I presents the performance comparison of the individual harmonic amplitude (peak value) using the conventional ADALINE-LMS and the proposed ADALINE-VSSLLMS algorithm. The harmonic component elimination that employs the ADALINE-VSSLLMS algorithm exhibits better precision than that, which uses the conventional approach. Moreover, the computational time needed for the proposed algorithm is lesser than that for the conventional one.

TABLE IPERFORMANCE COMPARISON

 

V. REAL-TIME FPGA IMPLEMENTATION

To evaluate the performance of the proposed ADALINE-VSSLLMS control algorithm applied for SHAPF, a prototype model is developed using a SPARTAN-3A XC3SD1800A DSP processor and is certified in the laboratory as shown in Fig. 9. The experimental setup is composed of an SKKD 101/16 diode bridge rectifier fed inductive load that acts as a nonlinear load. A balanced three-phase supply is fed to the load through an auto-transformer and IGBT module PM25RSB120, which acts as a voltage source inverter. In this experimental setup, the source inductor, filter inductor, filter capacitor, and DC-link capacitor are set as 120 μH, 1500 μH, 137 μF, and 2200 μF respectively. The load resistance and inductance values are 100 Ω and 36 mH, respectively. The switching frequency for the IGBT inverter is 10 KHz. LEM LV25-P and LEM LTS25-NP sensors are used to track the load currents and DC-link capacitor voltage, respectively. A signal conditioning circuit is designed to amplify and provide the necessary offset required by the analog to the digital converter circuit used. Table II describes the device utilization summary of the SPARTAN-3A XC3SD1800A DSP processor.

Fig. 9.Photograph of FPGA based experimental setup for implementing the proposed algorithm.

TABLE IIDEVICE UTILIZATION SUMMARY

Figs. 10(a) to (f) show the steady state waveforms of the three-phase source voltages, three-phase load currents, three-phase source currents, three-phase compensated currents, switching signals, and DC-link capacitor voltage, respectively. Fig. 10(f) indicates that the DC-link capacitor voltage is regulated with regard to its reference value, and the output current of PI controller is set as zero. These conditions satisfy the essential requirements of SHAPF. The reactive power and harmonic components of the load currents are almost compensated by the generated SHAPF currents depending on the feedback signal fed to the control circuit. Therefore, the source current waveforms are almost pure sinusoidal with an input power factor of 0.96.

Fig. 10.Experimental results of SHAPF under the steady state condition; (a) source voltages (va, vb, vc), (b) load currents (iLa, iLb, iLc), (c) source currents (isa, isb, isc), (d) compensating currents (ifa, ifb, ifc), (e) gating signals (ga, gb, gc), and (f) DC current (I0) and DC-link capacitor voltage (Vdc).

Figs. 11(a) to (c) demonstrate the experimental waveforms under the steady and dynamic states of load. The waveforms in each figure, from top to bottom, represent the source voltage va, source current isa, load current iLa, and filter current ifa, respectively. Fig. 11(b) shows the waveforms of SHAPF under the sudden changes of load from 2 KW to 1 KW, and Fig. 11(c) depicts the load changes from 1 KW to 2 KW. It has been observed that isa exhibits a fast transient response to settle down to a new value within a half-time period. The figures illustrate that both isa and Va are maintained with pure sinusoidal and same phase by employing the proposed control technique.

Fig. 11.Experimental waveforms of source voltage, source current, load current, and filter current (all values in phase-a); (a) steady state response of load, (b) and (c) dynamic response of SHAPF under sudden load variations (a) (b)

The harmonic spectra of iLa and isa are presented in Figs. 12(a) to (b), respectively. These figures indicate that the amplitude of the individual harmonics is reduced significantly by employing SHAPF based on the ADALINE-VSSLLMS control algorithm.

Fig. 12.Harmonic spectra; (a) load current, (b) source current.

 

VI. CONCLUSION

A novel mixed ADALINE-VSSLLMS control algorithm is presented for reference signal generation. The SHAPF based on proposed control algorithm has ability to compensate reactive power and eliminate harmonic components from the load currents. Both simulation and experimental results are analyzed to validate the efficacy of the proposed control algorithm. The findings reveal that the novel ADALINE-VSSLLMS approach is accurate, has fast convergence, and is stable at the dynamic changes of load in the power system. Given these advantages, the proposed control strategy can be a good solution for SHAPF, which requires adaptive characteristics and integrated functionalities.