References
- T. Park, H. J. Cho, J. D. Choe, I. H. Cho, D. Park, E. Yoon and J. H. Lee, "Characteristics of body-tied triple-gate pMOSFETs," IEEE Electron Dev. Lett. 25, pp. 798-800, December 2011.
- C.-W.Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J.-P Colinge, "Junctionless multigate field-effect transistor," Appl. Phys. Lett. 94, pp. 053511-1-053511-2, February 2009. https://doi.org/10.1063/1.3079411
- J. Rahul, S. Yadav, and V. K. Bohat, "Effects of metal gate electrode and HfO2 in junctionless vertical double gate MOSFET," Intl. Journal of Sci. Eng. And Tech. 3, pp. 671-674, May 2014.
- E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, "Theory of the junctionless nanowire FET," IEEE Electron Dev. Lett. 58, pp. 2903-2910, September 2011. https://doi.org/10.1109/TED.2011.2159608
- M. Wu, X. Jin, H. -I. Kwon, R. Chuai, X. Liu, and J. -H. Lee, "The optimal design of junctionless transistors with double-gate structure for reducing the effect of band-to-band tunneling," Journal of Semi. Tech. and Sci. 13, pp. 245-251, June 2013. https://doi.org/10.5573/JSTS.2013.13.3.245
- R. Rios, A. Cappellani, M. Armstrong, A. Budrevich, H. Gomez, R. Pai, N. Rahhal-orabi, and K. Kuhn, "Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm," IEEE Electron Dev. Lett. 32, pp. 1170-1172, September 2011. https://doi.org/10.1109/LED.2011.2158978
- S.-J. Choi, D. Moon, S. Kim, J.-H. Ahn, J.-S. Lee, J.-Y. Kim, and Y.-K. Choi, "Nonvolatile memory by all-around-gate junctionless transistor composed of silicon nanowire on bulk substrate," IEEE Electron Dev. Lett. 32, pp. 602-604, May 2011. https://doi.org/10.1109/LED.2011.2118734
- Y. Song, C. Zhang, R. Dowdy, K. Chabak, P. K. Mohseni, W. Choi, and X. Li, "III-V junctionless gate-all-around nanowire MOSFETs for high linearity low power applications," IEEE Electron Dev. Lett. 35, pp. 324-326, March 2014. https://doi.org/10.1109/LED.2013.2296556
-
S. Gundapaneni, S. Ganguly, and A. Kottantharayil, "Enhanced electrostatic integrity of short-channel junctionless transistor with high
${\kappa}$ spacers," IEEE Electron Dev. Lett. 32, pp. 1325-1327, October 2011. https://doi.org/10.1109/LED.2011.2162309 - M.-K. Jung, S.-H. Liu, J.-H. Ahn, K.-T. Lee, H.-S. Kang, Y.-W. Kim, and K.-P. Suh, "The influence of Cu diffusion on NMOS device characteristics," Journal of Kor. Phy. Soc. 40, pp. 692-696, April 2002. https://doi.org/10.3938/jkps.40.692