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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A Capacitorless Low-Dropout Regulator With Enhanced Response Time

응답 시간을 향상 시킨 외부 커패시터가 없는 Low-Dropout 레귤레이터 회로

  • Yeo, Jae-Jin (Dept. of Electronics and Communication Engineering, Hanyang University) ;
  • Roh, Jeong-Jin (Dept. of Electronics and Communication Engineering, Hanyang University)
  • Received : 2015.10.29
  • Accepted : 2015.12.01
  • Published : 2015.12.31
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Abstract

In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes $4.5{\mu}A$ quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a $0.11-{\mu}m$ CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of $0.8{\mu}s$ at maximum load current 200mA.

본 논문에서는 외부 커패시터가 없는 low-dropout (LDO) 레귤레이터를 설계하였으며, 대기 전류는 $4.5{\mu}A$ 이다. 제안하는 LDO 레귤레이터는 정밀한 로드 레귤레이션과 빠른 응답 속도를 만족하기 위해 두 개의 증폭기를 사용 하였고, 높은 이득을 갖는 증폭기와 빠른 속도 및 높은 슬루율을 가지는 증폭기로 구성 되어 있다. 이와 함께 패스 트랜지스터의 게이트에 존재하는 큰 기생 커패시터에 전류를 빠르게 충 방전시키기 위해, 전류 부스팅 회로를 추가하였다. 이를 통해 부하 전류 변화 시 응답 시간을 향상 시키게 된다. 설계된 회로는 $0.11-{\mu}m$ CMOS 공정으로 제작되었다. 최대 200mA 의 부하 전류를 구동할 수 있으며, 출력 전압 변동은 260mV, 회복 시간은 $0.8{\mu}s$ 을 측정하였다.

Keywords

References

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