JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

  • Li, Chang-Lin (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Hyun Joong (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Heo, Seo Weon (School of Electronics and Electrical Engineering, Hongik University) ;
  • Han, Tae Hee (College of Information and Communication Engineering, Sungkyunkwan University)
  • Received : 2015.08.24
  • Accepted : 2015.10.15
  • Published : 2015.12.30
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Abstract

Near-threshold computing (NTC) is now regarded as a promising candidate for innovative power reduction, which cannot be achieved with conventional super-threshold computing (STC). However, performance degradation and vulnerability to process variation in the NTC regime are the primary concerns. In this paper, we propose a voltage- and frequency-tuning methodology for mitigating the process-variation-induced problems in NTC-based manycore architectures. To implement the proposed methodology, we build up multiple-voltage multiple-frequency (MVMF) islands and apply a voltage-frequency tuning algorithm based on the critical-path monitoring technique to reduce the effects of process variation and maximize energy efficiency in the post-silicon stage. Experimental results show that the proposed methodology reduces overall power consumption by 8.2-20.0%, compared to existing methods in variation-sensitive NTC environments.

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References

  1. H. Esmaeilzadeh, et al, "Dark Silicon and the End of Multicore Scaling,'' Micro, IEEE, Vol.32, No.3, pp.122-134, Apr., 2012. https://doi.org/10.1109/MM.2012.17
  2. V. Govindaraju, C. H. Ho, and K. Sankaralingam, "Dynamically specialized datapaths for energy efficient computing," High Performance Computer Architecture, HPCA, 2011 IEEE 17th International Symposium on, pp.503-514, Feb., 2011.
  3. A. Raghavan, et al, "Computational Sprinting," High Performance Computer Architecture, HPCA, 2012 IEEE 18th International Symposium on, pp.1- 12, Feb., 2012.
  4. R. G. Dreslinski, et al, "Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits," Proceedings of the IEEE, Vol.98, No.2, pp.253-266, Feb., 2010. https://doi.org/10.1109/JPROC.2009.2034764
  5. U. R. Karpuzcu, N. S. Kim, and J. Torrellas, "Coping with Parametric Variation at Near-Threshold Voltages," Micro, IEEE, Vol.33, No.4, Jun., 2013.
  6. I. Stamelakos, et al, "Variation-Aware Voltage Island Formation for Power Efficient Near- Threshold Manycore Architectures," Design Automation Conference, ASP-DAC, 2014 19th Asia and South Pacific, pp.304-310, Jan., 2014.
  7. U. R. Karpuzcu, et al, "EnergySmart: Toward Energy-Efficient Manycores for Near-Threshold Computing," High Performance Computer Architecture, HPCA2013, 2013 IEEE 19th International Symposium on, pp.542-553, Feb., 2013.
  8. S. Rahimipour, et al, "A Survey of On-Chip Monitors," Circuits and Systems, ICCAS, 2012 IEEE International Conference on, pp.243-248, Oct., 2012.
  9. P. Ituero, et al, "Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration," Sensors Journal, IEEE, Vol.12 , No.6, Nov., 2011.
  10. Q. Z. Liu and S. S. Sapatnekar, "Capturing Post- Silicon Variations Using a Representative Critical Path," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol.29, No.2, Feb., 2010.
  11. C. R. Lefurgy, et al, "Active Guardband Management in Power7+ to Save Energy and Maintain Reliability," Micro, IEEE, Vol.33, No.4, pp.35-45, Apr., 2013. https://doi.org/10.1109/MM.2013.52
  12. A. Drake, et al, "A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor," Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, IEEE International, pp. 398 - 399, Feb., 2007.
  13. T. Sakurai and A. R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," Solid-State Circuits, IEEE Journal of, Vol.25, No.2, Apr., 1990.
  14. T. E. Carlson, W. Heirman, and L. Eeckhout, "Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulation," High Performance Computing, Networking, Storage and Analysis, SC, 2011 International Conference for, pp.1-12, Nov., 2011.
  15. S. Li, et al, "McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures," Microarchitecture, MICRO-42, 42nd Annual IEEE/ACM International Symposium on, pp.469-480, Dec., 2009.
  16. J. Torrellas, "Extreme-Scale Computer Architecture: Energy Efficiency from the Ground Up," Design, Automation and Test in Europe Conference and Exhibition, DATE 2014, pp.1-5, Mar., 2014.