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Pre-Packing, Early Fixation, and Multi-Layer Density Analysis in Analytic Placement for FPGAs

FPGA를 위한 분석적 배치에서 사전 패킹, 조기 배치 고정 및 밀도 분석 다층화

  • Kim, Kyosun (Department of Electronic Engineering, Incheon National University)
  • 김교선 (인천대학교 전자공학과)
  • Received : 2014.08.21
  • Accepted : 2014.09.26
  • Published : 2014.10.25

Abstract

Previous academic research on FPGA tools has relied on simple imaginary models for the targeting architecture. As the first step to overcome such restriction, the issues on analytic placement and legalization which are applied to commercial FPGAs have been brought up, and several techniques to remedy them are presented, and evaluated. First of all, the center of gravity of the placed cells may be far displaced from the center of the chip during analytic placement. A function is proposed to be added to the objective function for minimizing this displacement. And then, the density map is expanded into multiple layers to accurately calculate the density distribution for each of the cell types. Early fixation is also proposed for the memory blocks which can be placed at limited sites in small numbers. Since two flip-flops share control pins in a slice, a compatibility constraint is introduced during legalization. Pre-packing compatible flip-flops is proposed as a proactive step. The proposed techniques are implemented on the K-FPGA fabric evaluation framework in which commercial architectures can be precisely modeled, and modified for enhancement, and validated on twelve industrial strength examples. The placement results show that the proposed techniques have reduced the wire length by 22%, and the slice usage by 5% on average. This research is expected to be a development basis of the optimization CAD tools for new as well as the state-of-the-art FPGA architectures.

기존 학계의 FPGA 툴 연구는 단순한 가상 아키텍처 모델 가정에 의존해 왔다. 이러한 제약을 극복하기 위한 첫걸음으로 분석적 배치 및 배치 적법화의 기본 알고리즘들을 상용 FPGA의 아키텍처에 적용하는 실제 상황에서 발생되는 이슈들을 도출하여 대안을 제시한 후 그 효과를 평가하였다. 먼저, 코어 사용률이 낮은 FPGA에서 배치된 셀들의 무게 중심이 칩 중심에서 벗어나는 현상이 발생할 수 있는데 이 변위를 최소화하는 함수를 분석적 배치의 목적 함수에 추가하였다. 또한 배치 밀도 평가의 정확도를 높이기 위해 셀 종류별로 별도의 밀도 행렬을 사용하는 다층 분석, 그리고 자원이 매우 한정된 블록의 조기 고정 방안을 제안하였다. 그밖에, 슬라이스 내에서 두 개의 플립플롭이 제어 핀들을 공유하기 때문에 발생하는 호환성 문제를 개선하기 위한 플립플롭 사전 패킹도 제안하였다. 제안된 기법은 상용 FPGA 아키텍처를 정확하게 모델링하고 수정 개선할 수 있는 K-FPGA 패브릭 평가 툴킷을 근간으로 구현되었으며 12개의 실용 예제에 적용하여 기존 방식에 비해 평균적으로 배선길이 22%, 슬라이스 사용량 5%를 감축하는 효과를 확인하였다. 본 연구는 신규 FPGA 아키텍처 개발을 위한 최적화 CAD 툴 개발 연구의 기초가 될 것으로 기대한다.

Keywords

References

  1. ABC: A System for Sequential Synthesis and Verification. Berkeley Logic Synthesis and Verification Group, http://www.eecs.berkeley.edu/-alanmi/abc/abc.html, October, 2007.
  2. V. Betz and J. Rose, "VPR: A New Packing, Placement And Routing Tool For FPGA Research," in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications. pp.213-222, 1997.
  3. K. Kim, "Fabric Mapping and Placement of Field Programmable Stateful Logic Array," Journal of the IEEK, vol. 49, no. 12, pp. 1067-1076, December, 2012.
  4. N. Steiner, A. Wood, H. Shojaei, J. Couch, P. Athanas, M. French, "Torc: Towards Open-Source Tool Flow," in Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp.41-44, February, 2010.
  5. C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson, and B. Hutchings, "RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs" in Proceedings of the 21st International Workshop on Field-Programmable Logic and Applications, pp.349-355, September, 2011.
  6. K. Kim, "Evaluation Toolkit for K-FPGA Fabric Architectures," Journal of the IEEK, vol. 49-SD, no. 4, pp.157-167, April, 2012.
  7. Spartan-3 Generation FPGA User Guide, UG331, v1.6, Xilinx Inc., December 3, 2009.
  8. W.C. Naylor, R. Donelly, and L. Sha, "Non-Linear Optimization System and Method for Wire Length and delay Optimization for an Automatic Electric Circuit Placer," US Patent 6301693, October 2001.
  9. J. Cong and G. Luo, "Highly Efficient Gradient Computation for Density-Constrained Analytical Placement Methods," Proc. of the International Symposium on Physical Design, pp. 39-45, April, 2008.
  10. D.J.C. MacKay, "MacOpt-a Nippy Wee Optimizer," http://www.inference.phy.cam.ac.uk/mackay/c/macopt.html, June, 2004.
  11. X. Song, "Smoothing Method for Minimax Problems," Computational Optimization and Applications, Kluwer Academic Publishers, 20, pp.267-279, 2001.
  12. Xilinx Design Language Version 1.6, Xilinx, Inc., Xilinx ISE 6.1i Documentation in ise6.1i/help/data /xdl, July 2000.