Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Receiver for Dual-Channel CIS Interfaces

이중 채널 CIS 인터페이스를 위한 수신기 설계

  • Shin, Hoon (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Sang-Hoon (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kwon, Kee-Won (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Chun, Jung-Hoon (College of Information and Communication Engineering, Sungkyunkwan University)
  • 신훈 (성균관대학교 정보통신대학) ;
  • 김상훈 (성균관대학교 정보통신대학) ;
  • 권기원 (성균관대학교 정보통신대학) ;
  • 전정훈 (성균관대학교 정보통신대학)
  • Received : 2014.08.19
  • Accepted : 2014.09.30
  • Published : 2014.10.25
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Abstract

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

본 논문에서는 이중 채널 CIS(CMOS Image Sensor) 인터페이스를 위한 수신기 설계에 대해서 기술한다. 두 채널은 각각 CTLE(Continuous-Time Linear Equalizer)를 포함하며 샘플러, 병렬 변환기 그리고 clocking 회로로 구성되어 있다. Clocking 회로는 PLL, PI, CDR을 포함한다. CDR은 PI 기반이며 OSPD(Over Sampling Phase Detector)와 FSM(Finite State Machine)을 추가하여 빠른 락 소요 시간과 지연 시간, 향상된 jitter tolerance를 갖도록 하였다. CTLE는 3 GHz에서 -6 dB 손실을 갖는 채널의 ISI(Inter Symbol Interference)를 제거하며 CDR은 8000 ppm 이하의 주파수 오프셋에 대해 1 baud period 이내의 빠른 락 소요 시간을 갖는다. 65 nm CMOS 공정을 이용하여 설계하였으며 eye diagram에서 최소 368 mV의 전압 마진과 0.93 UI의 시간 마진을 갖는다.

Keywords

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