IEMEK Journal of Embedded Systems and Applications (대한임베디드공학회논문지)

Institute of Embedded Engineering of Korea (대한임베디드공학회)
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An Implementation of FPGA Embedded System for Real-Time SONAR Signal Display Using the Triple Buffering Method

삼중 버퍼링 방법을 이용한 실시간 소나 신호 디스플레이를 위한 FPGA 임베디드 시스템의 구현

  • Received : 2013.12.09
  • Accepted : 2014.03.04
  • Published : 2014.06.30
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Abstract

The CRT monitor display system for SONAR signal that are commonly used in ships or naval vessels uses vector scanning method. Therefore the processing circuits of the system are complex. Also the purchase of parts is difficult as well as high-cost because the production had been shut down. FPGA-based embedded system is flexible to various digital applications because it can be able to simplify processing circuits and to make a easy customized design for end user, and it provides low-cost high-speed performance. In this paper, we describe an implementation of FPGA embedded system for real-time SONAR signal display using the triple buffering method to overcome some weakness of existing CRT system. Our system provides real-time acquisition and display capability of SONAR signal, and removes afterimage effect that is a critical problem of the system proposed in the preceding study.

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References

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