• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.3
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• pp.173-182
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• 2014

The CRT monitor display system for SONAR signal that are commonly used in ships or naval vessels uses vector scanning method. Therefore the processing circuits of the system are complex. Also the purchase of parts is difficult as well as high-cost because the production had been shut down. FPGA-based embedded system is flexible to various digital applications because it can be able to simplify processing circuits and to make a easy customized design for end user, and it provides low-cost high-speed performance. In this paper, we describe an implementation of FPGA embedded system for real-time SONAR signal display using the triple buffering method to overcome some weakness of existing CRT system. Our system provides real-time acquisition and display capability of SONAR signal, and removes afterimage effect that is a critical problem of the system proposed in the preceding study.

• Journal of Contemporary Eastern Asia
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• v.13 no.1
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• pp.57-68
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• 2014

This paper positions the triple-Helix as a meso-level notion, an epicycle in a grander circle of technological change, institutional change, and psychological change. Because of the differing speeds of these several kinds of change, speed is proposed as a high-level system metric. This implies that what we commonly call bridging agencies or facilitators - lawyers, venture capitalists, incubators, etc. - are better called buffering agencies, as they help to engage entities changing at different speeds. They use human judgment as well as information technologies to choose feasible timing for these engagements. The paper highlights implications for thinking about innovation diffusion: The grand cycle of socio-technical change means we should, rather, think in terms of innovation reinforcement, or a circle of innovation.

• Asian Journal of Business Environment
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• v.2 no.2
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• pp.35-39
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• 2012

Purpose - Today's world is rapidly changing due to swift changes in organization's infrastructures and supply chain is becoming an important factor which affects the organization's global competitiveness. Research design / data / methodology - Researchers indicated that environment uncertainty is considered an external driving force to establish a unique supply chain. Market competition, reducing the gap of performance and quality between the products are compelling the practitioners and researcher to change the paradigm of managing the business processes effectively and efficiently. Results - In old times, supply chain of any organization was measured on the basis of inventory turns, defect rats, lead times, stock buffering and service level. But, Lee H.L. in 2004, published an article in Harvard Business Review who proposed three A (Adaptable, Agile and Aligned) termed as "Triple-A" of successful supply chain. Conclusions - He claimed that organizations can compete through the creation of Triple-A supply chain. Hence, the basic aim of this review paper is to develop basic insights regarding what is Triple-A of supply chain, its importance and functioning in today's competitive world.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.858-860
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• 2014

최근 영상처리 기법과 하드웨어의 발달로 의학 분야에서는 질병의 진단에 다양한 영상 시스템을 활용하고 있다. 특히 OCT 기술은 인체조직의 고해상도 이미지 획득과 혈류속도 측정을 동시에 할 수 있어 의료분야에 다양하게 적용이 가능하여 많은 관심을 받고 있다. 이에 더욱더 선명한 OCT 영상을 획득하기 위해 다양한 알고리즘과 필터를 사용함에 따라 빠른 프로세스 처리가 요구되고 있는 실정이다. 본 논문에서는 듀얼 코어 이상급의 CPU 를 탑재한 시스템에서 데이터 처리 모듈과 렌더링 모듈을 트리플 버퍼를 통해 비동기식으로 멀티스레드화 하였고, GPU 기반의 병렬처리를 통한 데이터 처리를 하여 속도를 향상시켰다. 이에 광학 카메라 촬영 시 선명한 실시간 OCT 영상을 확인할 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.