한국컴퓨터정보학회논문지 (Journal of the Korea Society of Computer and Information)

  • 제19권4호
  • /
  • Pages.1-8
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  • 2014
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  • 1598-849X(pISSN)
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  • 2383-9945(eISSN)
한국컴퓨터정보학회 (Korean Society of Computer Information)
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코어 내부 구성요소와 L2 캐쉬의 배치 관계에 따른 멀티코어 프로세서의 온도 분석

Analysis on the Temperature of Multi-core Processors according to Placement of Functional Units and L2 Cache

  • 손동오 (전남대학교 전자컴퓨터공학부) ;
  • 김종면 (울산대학교 전기공학부) ;
  • 김철홍 (전남대학교 전자컴퓨터공학부)
  • Son, Dong-Oh (School of Electronics and Computer Engineering, Chonnam National University) ;
  • Kim, Jong-Myon (School of Electrical Engineering, University of Ulsan) ;
  • Kim, Cheol-Hong (School of Electronics and Computer Engineering, Chonnam National University)
  • 투고 : 2013.11.20
  • 심사 : 2014.02.25
  • 발행 : 2014.04.30
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⟨ 이전 논문 다음 논문 ⟩

초록

멀티코어 프로세서는 여러 개의 코어가 하나의 칩에 배치됨에 따라 전력 밀도가 상승하여 높은 발열이 발생한다. 이러한 발열 문제를 해결하기 위해서 최근까지 다양한 연구가 진행되고 있다. 마이크로프로세서의 온도 감소를 위한 기법으로는 기계적 냉각 기법, 동적 온도 관리 기법 등이 있지만 이러한 기법들은 추가적인 냉각 비용이 발생하거나 성능의 저하가 발생한다. 플로어플랜기법은 추가적인 냉각비용이 발생하지 않으며, 성능저하가 거의 발생하지 않는다는 장점을 지닌다. 본 논문에서는 멀티코어 프로세서의 특정 구성요소의 발열 문제를 해결하기 위해 코어 내부 구성요소와 L2 캐쉬의 다양한 플로어플랜을 활용하고자 한다. 실험 결과, 코어의 뜨거운 구성요소를 L2 캐쉬와 인접하게 배치할 경우 칩의 온도 감소에 매우 효과적임을 알 수 있다. 코어를 캐쉬 상단-가운데 배치하는 기본 플로어플랜과 비교하여, 코어를 중앙에 배치하고 뜨거운 구성요소를 L2 캐쉬와 인접하게 배치하는 플로어플랜의 경우에는 $8.04^{\circ}C$, 코어를 외곽에 배치하고 뜨거운 구성요소를 L2 캐쉬와 인접하게 배치하는 플로어플랜의 경우에는 $8.05^{\circ}C$의 최고온도 감소 효과를 보임을 알 수 있다.

As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.

키워드

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