전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

자가보정 바이어스 기법을 이용한 Current Steering 10-bit CMOS D/A 변환기 설계

Design of a Current Steering 10-bit CMOS D/A Converter Based on a Self-Calibration Bias Technique

  • 임채열 (동국대학교 반도체과학과) ;
  • 이장우 (동국대학교 반도체과학과) ;
  • 송민규 (동국대학교 반도체과학과)
  • Lim, ChaeYeol (Department of Semiconductor Science, Dongguk University) ;
  • Lee, JangWoo (Department of Semiconductor Science, Dongguk University) ;
  • Song, MinKyu (Department of Semiconductor Science, Dongguk University)
  • 투고 : 2013.04.15
  • 발행 : 2013.10.25
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 NTSC/PAL 아날로그 TV를 구동하기 위한 10-bit current steering D/A 변환기를 제안하였다. 제안하는 D/A 변환기는 50MS/s 의 동작속도를 가지며, 6+4 분할 구조로 설계되었다. 또한 새로운 개념의 자가보정 바이어스 기법을 적용하여 칩 내부의 종단저항을 사용하고도 공정오차를 최소화 하였다. 제안하는 D/A 변환기는 3.3V 0.11um 1-poly 6-metal CMOS 공정을 사용하여 제작되었다. 제작된 칩의 유효 면적은 $0.35mm^2$, 3.3V 전원전압 상에서 약 88mW의 전력소모를 나타내었다. 실험 결과는 변환 속도 50MS/s, 입력 주파수 1MHz에서 SFDR 63.1dB의 특성을 나타내었다.

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is $0.35mm^2$ and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.

키워드

참고문헌

  1. G. Van der Plas, et al., "A 14-bit Intrinsic Accuracy Q2 Random Walk CMOS DAC," IEEE J. Solid-State Circuits, vol. 32, pp. 1708-1718, Dec. 1999.
  2. Yonghua Cong, et al., "A 1.5V 14b 100MS/s Self Calibrated DAC." ISSCC Dig. Tech. Papers, pp 128-129, Feb., 2003.
  3. A. Van den Bosch, et al., "SFDR Bandwidth Limitations for High Speed High Resolution Current Steering CMOS D/A Converters," Proc. ICECS, pp. 1193-1196, 1999.
  4. J. Hyde et al., "A 300-MS/s 14-bit Digital-to-Analog Converter in Logic CMOS," IEEE Journal of Solid-State Circuits, vol. 38, no. 5, pp. 734-740, May, 2003. https://doi.org/10.1109/JSSC.2003.810049
  5. Q. Huang et al., "A 200MS/s 14b 97mW DAC in 0.18um CMOS," ISSCC Dig. Tech. Papers, pp. 364-365, Feb., 2004.
  6. Luschas S., et al., "Output impedance requirements for DACs," Proceedings of the 2003 ISCAS, Volume:1, pp. I-512-515, May, 2003.
  7. Georgi I. Radulov et al., "An on-chip self-calibration method for current mismatch in D/A Converters," ESSCIRC,, pp. 169-172, Sept. 2005.
  8. Mikael Gustavsson, J. Jacob Wikner, Nianxiong Nick Tan, "CMOS Data Converters for Communications", Kluwer Academic Publishers., 2000, pp. 87-124
  9. Chi Hung Lin and Klaas Bult, "A 10-b 500Msample/s CMOS DAC in 0.6mm2" IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec. 1998. https://doi.org/10.1109/4.735535
  10. J. H. Kim and K. S. Yoon, "An 8-Bit CMOS 3.3V 65MHz Digital to Analog Converter with a Symmetric Two-Stage Current Cell Matrix Architecture" IEEE Trans. Circuits Systs.II, vol. 45, no. 12, pp. 1605-1609, Dec. 1998. https://doi.org/10.1109/82.746683
  11. J. H. Kim and K. S. Yoon, "An 8-Bit CMOS 3.3V 65MHz Digital to Analog Converter with a Symmetric Two-Stage Current Cell Matrix Architecture" IEEE Trans. Circuits Systs.II, vol.45, no. 12, pp. 1605-1609, Dec. 1998. https://doi.org/10.1109/82.746683
  12. Ueno, T. et al., "A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOS," CICC, pp. 747-750, Sept., 2005.
  13. M. Borremans, A. V. den Bosch, M. Steyaert, and W. Sansen, "A low power, 10-bit CMOS D/A converter for high speed applications," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), May 2001, pp. 157-160.
  14. Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey, "A 10-bit 80-MSPS 2.5-V 27.65-mW 0.185mm2 Segmented Current Steering CMOS DAC", VLDIS, 2005.
  15. Jurgen Deveugele, Member, IEEE, and Michiel S. J. Steyaert, "A 10-bit 250-MS/s Binary- Weighted Current-Steering DAC", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006
  16. Chi-Hung Lin and Klaas Bult, "A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998.
  17. Anne Van den Bosch, Marc A. F. Borremans, Michel S. J. Steyaert Senior, Willy Sansen,"A 10-bit 1-GSample/s Nyquist Current Steering CMOS D/A Converter", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 3, MARCH 2001.