The Journal of Korean Institute of Electromagnetic Engineering and Science (한국전자파학회논문지)

The Korean Institute of Electromagnetic Engineering and Science (한국전자파학회)
권호 표지
DOI QR코드

DOI QR Code

Novel Extraction Method for Unknown Chip PDN Using De-Embedding Technique

De-Embedding 기술을 이용한 IC 내부의 전원분배망 추출에 관한 연구

  • Kim, Jongmin (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, In-Woo (Samsung Electronics) ;
  • Kim, Sungjun (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, So-Young (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Nah, Wansoo (School of Information and Communication Engineering, Sungkyunkwan University)
  • 김종민 (성균관대학교 정보통신공학과) ;
  • 이인우 (삼성전자) ;
  • 김성준 (성균관대학교 정보통신공학과) ;
  • 김소영 (성균관대학교 정보통신공학과) ;
  • 나완수 (성균관대학교 정보통신공학과)
  • Received : 2013.03.11
  • Accepted : 2013.05.13
  • Published : 2013.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

GDS format files, as well as layout of the chip are noticeably needed so as to analyze the PDN (Power Delivery Network) inside of IC; however, commercial IC in the market has not supported design information which is layout of IC. Within this, in terms of IC having on-chip PDN, characteristic of inside PDN of the chip is a core parameter to predict generated noise from power/ground planes. Consequently, there is a need to scrutinize extraction method for unknown PDN of the chip in this paper. To extract PDN of the chip without IC circuit information, the de-embedding test vehicle is fabricated based on IEC62014-3. Further more, the extracted inside PDN of chip from de-embedding technique adopts the Co-simulation model which composes PCB, QFN (Quad-FlatNo-leads) Package, and Chip for the PDN, applied Co-simulation model well corresponds with impedance from measured S-parameters up to 4 GHz at common measured and simulated points.

IC 내부의 전원분배망(PDN: Power Delivery Network) 회로를 분석하기 위해서는 IC의 디자인 정보가 담긴 파일이 필요하지만, 상용 IC(Commercial IC)의 경우 보안상의 이유로 디자인 정보를 제공하지 않고 있다. 하지만 온-칩 전원분배망(On-chip PDN) 특성이 포함된 경우에는 PCB와 패키지의 특성만으로는 정확한 해석이 어려우므로 본 연구에서는 IC 내부의 정보가 제공하지 않는 전원분배망(PDN) 회로의 추출에 관하여 연구를 하였다. IC 내부의 전원분배망(PDN)의 주파수에 대한 특성을 추출하기 위하여, IEC62014-3에서 제안하고 있는 추출용 보드를 제작하였고, 추출용 보드를 구성하고 있는 SMA 커넥터, 패드, 전송 선로, 그리고 QFN 패키지의 주파수에 대한 특성들을 분석하였다. 추출된 결과들은 디임베딩(de-embedding) 기술에 적용하여 IC 내부의 전원분배망(PDN) 회로를 S-parameter 기반으로 모델을 추출하였고, 평가용 보드의 전원분배망 결합회로(PDN Co-simulation)모델에 적용하여 측정과 비교한 결과, ~4 GHz까지 잘 일치하였다.

Keywords

References

  1. J. Choi, S. H. Min, J. H. Kim, and M. Swaminathan, "Modeling and analysis of power distribution networks for gigabit application", IEEE Trans. Mobile Computing, vol. 2, no. 4, pp. 299-312, Oct. 2003. https://doi.org/10.1109/TMC.2003.1255645
  2. M. S. Gupta, J. L. Oatley, R. Joseph, G. Y. Wei, and D. M. Brooks, "Understanding voltage variations in chip multiprocessors using a distributed power-delivery network", Proceeding of the Conference on Design, Automation and Test in Europe, pp. 624-629, 2007.
  3. M. Swaminathan, A. E. Engin, Power Integrity Modeling and Design for Semiconductors and Systems, Prentice Hall, 2008.
  4. J. H. Kim, M. Swaminathan, "Modeling of irregular shaped power distribution planes using transmission matrix method", IEEE Trans. Advanced Packaging, vol. 24, no. 3, Aug. 2001.
  5. J. Kim, K. J. Song, J. Yoo, and W. Nah, "Analysis of coupled simultaneous switching noise induced from power delivery network in adjacent switching circuit", IEEE Electronics Packaging Technology Conf., pp. 968-972, Dec. 2009.
  6. N. Na, M. Swaminathan, "Modeling and simulation of planes in electronic packages for GHz systems", IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 149-152, Oct. 1999.
  7. S. Chun, M. Swaminathan, L. D. Smith, J. Srinivasan, Z. Jin, and M. K. Lyer, "Modeling of simultaneous switching noise in high speed systems", IEEE Trans. Advanced Packaging, vol. 24, no. 2, pp. 132-142, May 2001. https://doi.org/10.1109/6040.928747
  8. J. Kim, W. Lee, Y. Shim, J. Shim, K. Kim, J. S. Pak, and J. Kim, "Chip-package hierarchical power distribution network modeling and analysis based on a segmentation method", IEEE Trans. Advanced Packaging, vol. 33, no. 3, pp. 647-659, Aug. 2010. https://doi.org/10.1109/TADVP.2010.2043673
  9. W. Cheng, A. Sarkar, S. Lin, and J. Zheng, "Worst case switching pattern for core noise analysis", DesignCon, 2009.
  10. IEC62014-3 : EMC for Component-Part 3: Integrated Circuits Electrical Model (ICEM).
  11. H. H. Park, S. H. Song, S. T. Han, T. S. Jang, J. H. Jung, and H. B. Park, "Estimation of power switching current by chip-package-PCB cosimulation", IEEE Trans. Electromagnetic Compatibility, vol. 52, no. 2, pp. 311-319, May 2010. https://doi.org/10.1109/TEMC.2010.2043255
  12. T. Steinecke, H. Koehne, and M. Schmidt, "Behavioral EMI models of complex digital VLSI circuits", Microelectronics Journal, no. 35, pp. 547-555, 2004.
  13. J. L. Levant, M. Ramdani, R. Perdriau, and M. Drissi, "EMC assessment at chip and PCB level: use of the ICEM model for jitter analysis in an integrated PLL", IEEE Trans. Electromagnetic Compatibility, vol. 49, no. 1, pp. 182-191, Feb. 2007. https://doi.org/10.1109/TEMC.2006.888181
  14. C. H. Chen, M. J. Deen, "A general noise and S-parameter deembedding procedure for on-wafer high-frequency noise measurements of MOSFETs", IEEE Trans. Microwave Theory and Techniques, vol. 49, no. 5, pp. 1004-1005, May 2001. https://doi.org/10.1109/22.920164
  15. M. H. Cho, G. W. Huang, Y. H. Wang, and L. K. Wu, "A scalable noise de-embedding technique for on-wafer microwave device characterization", IEEE Microwave and Wireless Components Letters, vol. 15, no. 10, pp. 649-651, Oct. 2005. https://doi.org/10.1109/LMWC.2005.856685
  16. F. Guo, M. Frankovich, "On-die decoupling capacitor measurement using vector network analyzer", IEEE Electrical Performance of Electronic Packaging Conf., pp. 25-28, Oct. 2006.
  17. I. S. Stievano, I. A. Maio, L. Rigazio, F. G. Canavero, R. Izzi, A. Girardi, T. Lessio, A. Conci, T. Cunha, H. Teixeira, and J. C. Pedro, "Characterization and modeling of the power delivery networks of memory chips", IEEE Signal Propagation on Interconnects Conf., pp. 1-4, May 2009.