JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

  • Seo, Jin-Cheol (Department of Electronics Engineering, Inha University) ;
  • Moon, Yong-Hwan (Department of Electronics Engineering, Inha University) ;
  • Seo, Joon-Hyup (Department of Electronics Engineering, Inha University) ;
  • Jang, Jae-Young (Department of Electronics Engineering, Inha University) ;
  • An, Taek-Joon (Department of Electronics Engineering, Inha University) ;
  • Kang, Jin-Ku (Department of Electronics Engineering, Inha University)
  • Received : 2012.08.29
  • Accepted : 2013.03.01
  • Published : 2013.06.30
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Abstract

In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7, and 5.4 Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit covers three different operating frequencies with a single VCO switching the operating frequency by the 3-bit digital code. The prototype chip has been designed and verified using a 65 nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4 Gbps at $2^{31}$-1 PRBS is measured to 7/5.6/4.7 $ps_{rms}$, respectively, while consuming 11 mW from a 1.2 V supply.

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References

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