The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Low-power Butterfly Structure for DIT Radix-4 FFT Implementation

DIT Radix-4 FFT 구현을 위한 저전력 Butterfly 구조

  • 장영범 (상명대학교 정보통신공학과) ;
  • 이상우 (상명대학교 정보통신공학과)
  • Received : 2013.11.11
  • Accepted : 2013.12.05
  • Published : 2013.12.31
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Abstract

There are two FFT(Fast Fourier Transform) algorithms, which are DIT(Decimation-In-Time) and DIF(Decimation-In- Frequency). Even the DIF algorithm is more widely used because of its various implementation architectures, the DIT structures have not been investigated. In this paper, the DIT Radix-4 algorithm is derived and its efficient butterfly structure is proposed for SoC(System on a Chip) implementation.

FFT(Fast Fourier Transform) 알고리즘에는 DIT(Decimation-In-Time)와 DIF(Decimation-In-Frequency)가 있다. DIF 알고리즘은 Radix-2/4/8 등의 다양한 종류와 그 구현 방법이 개발되어 사용되는데 반하여 DIT 알고리즘은 순차적인 출력을 낼 수 있는 장점에도 불구하고 다양한 구현방법이 연구되지 못하였다. 이 논문에서는 DIT Radix-4 알고리즘을 유도하며 반도체 구현을 위한 효율적인 butterfly 구조를 제안한다.

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References

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