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CMOS Rectifier for Wireless Power Transmission Using Multiplier Configuration

Multiplier 설정을 통한 무선 전력 전송 용 CMOS 정류 회로

  • Jeong, Nam Hwi (School of Electronics, Telecommunication and Computer Engineering, Korea Aerospace university) ;
  • Bae, Yoon Jae (School of Electronics, Telecommunication and Computer Engineering, Korea Aerospace university) ;
  • Cho, Choon Sik (School of Electronics, Telecommunication and Computer Engineering, Korea Aerospace university)
  • 정남휘 (한국항공대학교 항공전자 및 정보통신공학부) ;
  • 배윤재 (한국항공대학교 항공전자 및 정보통신공학부) ;
  • 조춘식 (한국항공대학교 항공전자 및 정보통신공학부)
  • Received : 2013.07.23
  • Accepted : 2013.11.27
  • Published : 2013.12.25

Abstract

We present a rectifier for wireless power transmission using multiplier configuration in layout for MOSFETs which works at 13.56 MHz, designed to fit in CMOS process where conventionally used diodes are replaced with the cross-coupled MOSFETs. Full bridge rectifier structure without comparators is employed to reduce current consumption and to be working up to higher frequency. Multiplier configuration designed in layout reduces time delay originated from parasitic series resistance and shunt capacitance at each finger due to long connecting layout, leading to fast transition from on-state to off-state cross-coupled circuit structure and vice versa. The power conversion efficiency is significantly increased due to this fast transition time. The rectifier is fabricated in $0.11{\mu}m$ CMOS process, RF to DC power conversion efficiency is measured as 86.4% at the peak, and this good efficiency is maintained up to 600 MHz, which is, to our best knowledge, the highest frequency based on cross-coupled configuration.

우리는 MOSFET Layout 단계에서 Multiplier 구성을 통한 Common centroid layout 방식을 사용한 무선 전력 전송 용 CMOS 정류회로를 제안한다. 제안하는 정류회로는 기존의 다이오드를 사용하지 않은 Cross-coupled MOSFET 정류회로로 13.56 MHz에서 동작한다. 전력 소모를 최소화하고, 높은 주파수까지 동작하기 위하여 Full bridge 정류회로에서 효율을 높이기 위한 비교기를 제거하였다. Layout 단계에서 Multiplier 구성을 통한 Common centroid layout 방식은 Chip-layout 상에서 MOSFER의 Finger에 의해 길어진 연결 선로에 존재하는 기생 직렬 저항과 병렬 Capacitor에 의해 발생하는 시간 지연을 줄이기 위해 고안되어, 천이 시간을 줄여 Cross-coupled 구조의 On-상태에서 Off-상태, 혹은 그 반대의 상태 변화를 빠르게 한다. 이는 빠른 상태 변화 시간으로 인해 전력 변환 효율을 증가시킨다. 본 정류회로는 $0.11{\mu}m$ CMOS 공정으로 제작되었으며, 전력 변환 효율은 최대 86.4%로 측정되었으며, 600 MHz 이상까지 높은 전력 변환 효율을 가지며, 이는 현재 발표된 것 중, Cross-coupled 구성을 기반으로 한 정류회로 중 가장 높은 성능을 가진다.

Keywords

References

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