JSTS:Journal of Semiconductor Technology and Science

  • 제12권3호
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  • Pages.360-369
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  • 2012
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

  • Lee, Myoung-Sun (Inter -University Semiconductor Research Center (ISRC), and School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Joe, Sung-Min (Inter -University Semiconductor Research Center (ISRC), and School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Yun, Jang-Gn (Semiconductor R&D Center of Samsung Electronics Company Ltd.) ;
  • Shin, Hyung-Cheol (Inter -University Semiconductor Research Center (ISRC), and School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Park, Byung-Gook (Inter -University Semiconductor Research Center (ISRC), and School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Park, Sang-Sik (Department of Electronics Engineering, Sejong University) ;
  • Lee, Jong-Ho (Inter -University Semiconductor Research Center (ISRC), and School of Electrical Engineering and Computer Science, Seoul National University)
  • 투고 : 2011.10.31
  • 발행 : 2012.09.30
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초록

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

키워드

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