The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Design of a CMOS Single Bit 3rd Order Delta-Sigma Modulator with Switched Operational Amplifier

스위치드 연산증폭기를 이용한 CMOS 단일비트 3차 델타시그마 변조기 설계

  • 이한울 (인하대학교 아날로그집적회로설계 연구실) ;
  • 시대 (인하대학교 아날로그집적회로설계 연구실) ;
  • 유태경 (인하대학교 아날로그집적회로설계 연구실) ;
  • 이건 (인하대학교 아날로그집적회로설계 연구실) ;
  • 윤광섭 (인하대학교 전자공학과) ;
  • 이상민 (인하대학교 전자공학과)
  • Received : 2011.10.21
  • Accepted : 2012.07.06
  • Published : 2012.08.31
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Abstract

This paper presents Single-bit Third order Delta-Sigma Modulator, which can be applied to the Low speed High resolution ADC in Audio signal Process System. Whereas the Operational Amplifier in modulator consumed static power dissipation in operating, this modulator used Switching on/off techniques, which makes the Power dissipation of the modulator reduced. Also proposed modulator minimizes frequency characteristic variation by optimizing switch position. And this modulator chooses Single-bit type to guarantee stability. The designed ADC went through 0.35um CMOS n-well 1-poly 4-metal process to be a final product, and the final product has shown 17.1mW of power dissipation with 3.3V of Supply Voltage, 6.4MHz of conversion rate. And 84.3dB SNDR and 13.5bit ENOB with 20KHz of input frequency.

본 논문은 오디오 신호 처리 시스템의 저속 고해상도 ADC를 위해 설계된 CMOS 단일비트 3차 델타시그마 변조기를 설계하였다. 변조기 내 적분기에 사용되는 연산증폭기의 전력소모를 감소시키기 위해서 연산증폭기내 바이어스 전류원에 차단/동작 기능을 하는 스위치를 장착시켰다. 또한 변조기내 스위치의 위치를 최적화 하여 기존의 스위칭 방식에서 발생하는 주파수 특성 변화를 최소화하였다. 단일 비트 3차 델타시그마 변조기 구조를 선택하였으며, 제안한 델타 시그마 변조기의 성능측정결과 전원 전압 3.3V, 샘플링 주파수 6.4MHz, 입력주파수 20KHz에서 17.1mW의 전력소모를 나타냈다. SNDR은 84.3dB, 유효비트수는 13.5비트를 나타내었다.

Keywords

References

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