Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low Area Design and Implementation for IEEE 802.11a OFDM Timing Synchronization Block

IEEE 802.11a OFDM 타이밍 동기화기 블록의 저면적 설계 및 구현

  • 석상철 (상명대학교 컴퓨터정보통신공학과) ;
  • 장영범 (상명대학교 컴퓨터정보통신공학과)
  • Received : 2011.09.05
  • Accepted : 2012.02.15
  • Published : 2012.02.25
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Abstract

In this paper, a low area timing synchronization structure for the IEEE 802.11a OFDM MODEM SoC is proposed. The timing synchronization block of the IEEE 802.11a OFDM MODEM SoC requires large implementation area. In the proposed timing synchronization structure, it is shown that the number of multiplication can be reduced by using the transposed direct form filter. Furthermore, implementation area of the proposed structure can be more reduced using CSD(Canonic Signed Digit) and Common Sub-expression Sharing techniques. Through Verilog-HDL coding and synthesis, it is shown that the 22.7 % of implementation area can be reduced compared with the conventional one.

이 논문에서는 IEEE 802.11a OFDM MODEM SoC용 타이밍 동기화 블록에 대한 저면적 구조를 제안한다. IEEE 802.11a의 타이밍 동기화 블록은 큰 구현 면적을 필요로 한다. 제안된 자기 상관 방식의 타이밍 동기화 블록 구조는 전치 직접형 필터 구조를 사용하여 곱셈 연산을 최소화하였다. 또한 CSD(Canonic Signed Digit) 계수를 이용하는 기술과 Common Sub-expression Sharing 기술을 적용하여 곱셈연산을 저면적으로 구현하였다. 제안된 타이밍 동기화 블록 구조에 대하여 Verilog-HDL 코딩과 0.13 micron 공정을 사용하여 합성한 결과, 기존 구조와 비교하여 22.7%의 구현 면적 감소 효과를 얻을 수 있었다.

Keywords

References

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