• Journal of Information Processing Systems
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• v.15 no.4
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• pp.890-903
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• 2019

The single carrier frequency domain equalization (SC-FDE) technology is an important part of the broadband wireless access communication system, which can effectively combat the frequency selective fading in the wireless channel. In SC-FDE communication system, the accuracy of timing synchronization directly affects the performance of the SC-FDE system. In this paper, on the basis of Schmidl timing synchronization algorithm a timing synchronization algorithm suitable for FPGA (field programmable gate array) implementation is proposed. In the FPGA implementation of the timing synchronization algorithm, the sliding window accumulation, quantization processing and amplitude reduction techniques are adopted to reduce the complexity in the implementation of FPGA. The simulation results show that the algorithm can effectively realize the timing synchronization function under the condition of reducing computational complexity and hardware overhead.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.1
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• pp.99-108
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• 1999

In this paper, we propose $\pi$/4 QPSK scheme with block modulation algorithm, which can reduce preamble in order to transmit ATM cell efficiently in the uplink channel of LMDS, and also designed a new carrier recovery circuit which can improve carrier synchronization performance of block demodulation algorithm. The $\pi$/4 QPSK scheme employing the proposed block modulation algorithm achieved efficient frame transmission by making use of a few preamble when carrier synchronization, symbol timing synchronization and slot timing synchronization were performed by burst data of ATM cell in LMDS environment. For performance evaluation of the proposed method, a simulation analyzing the variation of carrier synchronization, symbol timing synchronization and slot timing synchronization using LMDS environment and burst mode condition was executed. In the simulation, the proposed method showed a good performance even though the reduced preamble as a few aspossible when carrier synchronization, symbol timing synchronization and slot timing synchronization is performed.

• Journal of Communications and Networks
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• v.14 no.5
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• pp.501-509
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• 2012

This paper proposes a joint timing synchronization, channel estimation, and data detection for the impulse radio ultra-wideband systems. The proposed timing synchronizer consists of coarse and fine timing estimation. The synchronizer discovers synchronization points in two stages and performs adaptive threshold based on the maximum pulse averaging and maximum (MAX-PA) method for more precise synchronization. Then, iterative channel estimation is performed based on the discovered synchronization points, and data are detected using the selective rake (S-RAKE) detector employing maximal ratio combining. The proposed synchronizer produces two signals-the start signal for channel estimation and the start signal for start frame delimiter (SFD) detection that detects the packet synchronization signal. With the proposed synchronization, channel estimation, and SFD detection, an S-RAKE receiver with binary pulse position modulation binary phase-shift keying modulation was constructed. In addition, an IEEE 802.15.4a channel model was used for performance comparison. The comparison results show that the constructed receiver yields high performance close to perfect synchronization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.31-38
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• 2012

In this paper, a low area timing synchronization structure for the IEEE 802.11a OFDM MODEM SoC is proposed. The timing synchronization block of the IEEE 802.11a OFDM MODEM SoC requires large implementation area. In the proposed timing synchronization structure, it is shown that the number of multiplication can be reduced by using the transposed direct form filter. Furthermore, implementation area of the proposed structure can be more reduced using CSD(Canonic Signed Digit) and Common Sub-expression Sharing techniques. Through Verilog-HDL coding and synthesis, it is shown that the 22.7 % of implementation area can be reduced compared with the conventional one.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.9
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• pp.1038-1040
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• 2016

This paper introduces a fine timing synchronization based on reference signals. The proposed method first estimates a channel impulse response (CIR), and acquires the timing offset based on the change point of statistics of the estimated CIR. It is confirmed that the proposed estimator can significantly improve the fine timing synchronization performance compared to conventional schemes over diverse channel environments.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.55-61
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• 2007

In this paper, we represent the maximum detection probability formulas of symbol synchronization timing at each received delay signal in multipath channel delay profile in the multiplied correlation and difference type correlated symbol synchronization timing detection method. The computer simulation results show that the correlation symbol timing detection method have maximum detection probability at the lead of received delay signal of highest amplitude, but the difference type of correlation symbol timing detection method always have maximum detection probability at the lead of first received delay signal in the multipath channel models. Using this results, we show the BER characteristics difference between the IEEE802.11a OFDM signals which is obtained in case of the symbol synchronization timing is taken at zero error(perfect) timing position and at -1 sample error symbol timing position from perfect timing position in the multipath channel models regardless the length of channel delay spread.

• Journal of Positioning, Navigation, and Timing
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• v.3 no.4
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• pp.163-170
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• 2014

A pseudolite is used as a GPS backup system, and is also used for the purpose of indoor navigation and correction information transmission. It is installed on the ground, and transmits signals that are similar to those of a GPS satellite. In addition, in recent years, studies on the improvement of positioning accuracy using the pseudorange measurement of a pseudolite have been performed. As for the effect of the time synchronization error between a pseudolite and a GPS satellite, a time synchronization error of 1 us generally induces a pseudorange error of 300 m; and to achieve meter-level positioning, ns-level time synchronization between a pseudolite and a GPS satellite is required. Therefore, for the operation of a pseudolite, a time synchronization algorithm between a GPS satellite and a pseudolite is essential. In this study, for the time synchronization of a pseudolite, "a pseudolite time synchronization method using the time source of UTC (KRIS)" and "a time synchronization method using a GPS timing receiver" were introduced; and the time synchronization performance depending on the pseudolite time source and reference time source was evaluated by designing a software-based pseudolite time synchronization performance evaluation simulation platform.

• Journal of the Korea Society of Computer and Information
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• v.20 no.8
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• pp.23-28
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• 2015

TPSN(Timing-sync Protocol for Sensor Networks), the representative of time synchronization protocol for WSN(wireless sensor networks), was developed to provide higher synchronization accuracy and energy efficiency. So, TPSN's approach has been referenced by so many other WSN synchronization schemes till now. However, TPSN has a collision problem due to simultaneous transmission among competing nodes, which causes more network convergence delay for a network-wide synchronization. A Polling-based scheme for TPSN is proposed in this paper. The proposed scheme not only shortens network-wide synchronization time of TPSN, but also reduce collision traffic which lead to needless power consumption. The proposed scheme's performance has been evaluated and compared with an original scheme by simulation. The results are shown to be better than the original algorithm used in TPSN.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11A
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• pp.1124-1131
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• 2008

In this paper, we propose a timing synchronization scheme and its hardware architecture of the next generation IEEE 802.11n wireless LAN standard which is based on MIMO-OFDM technique. Proposed timing synchronization method takes two steps which consist of two modified auto-correlators. For coarse timing synchronization, a sliding window differentiator is used after a conventional auto-correlation in order to avoid plateau problem. The conjugate symmetry property of L-LTS is utilized for the simplification of fine timing synchronization. Since cross-correlation based methods are not required, the computational complexity and the number of multipliers can be reduced. In order to reduce the hardware complexity, we have used sign multipliers. Based on simulation results, the proposed method outperforms a conventional method. The proposed scheme can be applied to IEEE 802.11n systems and can easily be expanded to frequency synchronization scheme.