JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A 40fJ/c-s 1 V 10 bit SAR ADC with Dual Sampling Capacitive DAC Topology

  • Received : 2010.11.24
  • Accepted : 2011.01.05
  • Published : 2011.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

A 40 fJ/c-s, 1 V, 10-bit SAR ADC is presented for energy constrained wearable body sensor network application. The proposed 10-bit dual sampling capacitive DAC topology reduces switching energy by 62% compared with 10-bit conventional SAR ADC. Also, it is more robust to capacitor mismatch than the conventional architecture due to its cancelling effect of each capacitive DAC. The proposed SAR ADC is fabricated in 0.18 ${\mu}m$ 1P6M CMOS technology and occupies 1.17 $mm^2$ including pads. It dissipates only 1.1 ${\mu}W$ with 1 V supply voltage while operating at 100 kS/s.

Keywords

References

  1. Long Yan, Jerald Yoo, Binhee Kim and Hoi-Jun Yoo, "A $0.5{\mu}V_{rms}12{\mu}W$ patch type fabric sensor for wearable body sensor network,〃 IEEE A-SSCC, pp.105-108, Nov., 2009. https://doi.org/10.1109/ASSCC.2009.5357190
  2. Jerald Yoo, Long Yan, Seulki Lee, Yongsang Kim and Hoi-Jun Yoo, "A 5.2 mW Self-Configured Wearable Body Sensor Network Controller and a $12{\mu}W$ 54.9% Efficiency Wirelessly Powered Sensor for Continuous Health Monitoring System,〃 IEEE J. Solid-State Circuits, Vol.45, pp.178-188, Jan., 2010. https://doi.org/10.1109/JSSC.2009.2034440
  3. Rafal, Dlugosz, and K. Iniewski, “Flexible architecture of ultralow-power current-mode interleaved successive approximation analog-to digital converter for wireless sensor networks,” VLSI Design, 2007, Apr. 2007.
  4. N. Verma and A.C Chandrakasan, “A $25{\mu}W$ 100 kS/s 12b ADC for wireless application,” IEEE International Solid State Circuits., Conference Dig. Tech. Papers(ISSCC), pp.222-223, Feb., 2006.
  5. James L.Mccreary et al, "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part I," IEEE J. Solid-State Circuits, pp.371-379, Dec., 1975. https://doi.org/10.1109/JSSC.1975.1050629
  6. Brian P. Ginsburg and Anantha P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC,” IEEE J. Solid-State Circuits, Vol.42, No.4, pp.739-747, Apr., 2007. https://doi.org/10.1109/JSSC.2007.892169
  7. Brian P. Ginsburg and Anantha P. Chandrakasan, "An Energy- Efficient Charge Recycling Approach for a SAR Converter With Capacitive DAC," in Proc. IEEE Int. Symp. Circuits and Systems, 2005, Vol.1, pp.184-187, May., 2005. https://doi.org/10.1109/ISCAS.2005.1464555

Cited by

  1. An efficient threshold voltage generation for SAR ADCs vol.75, pp.1, 2013, https://doi.org/10.1007/s10470-013-0028-8
  2. A 0.16㎟ 12b 30MS/s 0.18um CMOS SAR ADC Based on Low-Power Composite Switching vol.53, pp.7, 2016, https://doi.org/10.5573/ieie.2016.53.7.027