한국통신학회논문지 (The Journal of Korean Institute of Communications and Information Sciences)

  • 제36권3C호
  • /
  • Pages.175-182
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  • 2011
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  • 1226-4717(pISSN)
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  • 2287-3880(eISSN)
한국통신학회 (The Korean Institute of Commucations and Information Sciences)
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효율적인 파이프라인 구조와 스케줄링 기법을 적용한 고속 8-병렬 FFT/IFFT 프로세서

High Speed 8-Parallel Fft/ifft Processor using Efficient Pipeline Architecture and Scheduling Scheme

  • 김은지 (아주대학교 정보통신대학 전자공학부) ;
  • 선우명훈 (아주대학교 정보통신대학 전자공학부)
  • 투고 : 2011.01.17
  • 심사 : 2011.02.17
  • 발행 : 2011.03.31
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초록

본 논문에서는 고속 데이터 전송을 위해 OFDM 시스템에 적용 가능한 고속 FFT/IFFT 프로세서를 제안하였다. 제안하는 프로세서는 높은 데이터 처리율을 만족하기 위해서 MDC 구조와 다중 병렬 처리 기법을 채택하였다. 하드웨어 복잡도를 줄이기 위해서 본 논문에서는 연산에 필요한 연산기의 수를 줄이는 구조로 버터플라이 연산기의 수를 줄인 MRMDC 구조와 효율적인 스케줄링 기법을 적용하여 복소 곱셈기의 수를 줄이는 구조를 제안한다. 제안하는 구조를 적용함으로써 연산 싸이클을 증가시키지 않고 하드웨어 복잡도를 줄일 수 있다. UWB, WiMAX, O-OFDM과 같은 고속 OFDM 시스템을 위해 제안하는 프로세서는 128-포인트와 256-포인트 두 가지 모드를 지원 가능하다. 제안하는 프로세서는 IBM 90nm 공정으로 합성하여 메모리를 제외한 전체 게이트 수가 760,000개를 보이며, 동작속도는 430MHz를 나타내었다.

This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a high throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a modified mixed-radix multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the number of complex multipliers at the second stage from 88 to 40. The proposed FFT/IFFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT/IFFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.

키워드

참고문헌

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