JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A Unified Analytical One-Dimensional Surface Potential Model for Partially Depleted (PD) and Fully Depleted (FD) SOI MOSFETs

  • Pandey, Rahul (Department of Electrical Engineering Indian Institute of Technology) ;
  • Dutta, Aloke K. (Department of Electrical Engineering Indian Institute of Technology)
  • Received : 2011.03.21
  • Published : 2011.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this work, we present a unified analytical surface potential model, valid for both PD and FD SOI MOSFETs. Our model is based on a simplified one dimensional and purely analytical approach, and builds upon an existing model, proposed by Yu et al. [4], which is one of the most recent compact analytical surface potential models for SOI MOSFETs available in the literature, to improve its accuracy and remove its inconsistencies, thereby adding to its robustness. The model given by Yu et al. [4] fails entirely in modeling the variation of the front surface potential with respect to the changes in the substrate voltage, which has been corrected in our modified model. Also, [4] produces self-inconsistent results due to misinterpretation of the operating mode of an SOI device. The source of this error has been traced in our work and a criterion has been postulated so as to avoid any such error in future. Additionally, a completely new expression relating the front and back surface potentials of an FD SOI film has been proposed in our model, which unlike other models in the literature, takes into account for the first time in analytical one dimensional modeling of SOI MOSFETs, the contribution of the increasing inversion charge concentration in the silicon film, with increasing gate voltage, in the strong inversion region. With this refinement, the maximum percent error of our model in the prediction of the back surface potential of the SOI film amounts to only 3.8% as compared to an error of about 10% produced by the model of Yu et al. [4], both with respect to MEDICI simulation results.

Keywords

References

  1. Y. Choi, D. Ha, T. King, and C. Hu, "Nanoscale ultrathin body PMOSFETs with raised selective Germanium source/drain", IEEE Electron Device Letters, Vol.22, No.9, pp.447-448, Sep., 2001. https://doi.org/10.1109/55.944335
  2. J.P. Colinge, "Subthreshold slope of thin-film SOI MOSFETs", IEEE Electron Device Letters, Vol.7, No.4, pp.244-246, Apr., 1986. https://doi.org/10.1109/EDL.1986.26359
  3. H. Lim and J.G. Fossum, "Threshold voltage of thin-film Silicon-on-Insulator (SOI) MOSFETs", IEEE Transactions on Electron Devices, Vol.30, No.10, pp.1244-1251, Oct., 1983. https://doi.org/10.1109/T-ED.1983.21282
  4. Y.S. Yu, S.H. Kim, S.W. Hwang, and D. Ahn, "All analytic surface potential model for SOI MOSFETs", IEE Proceedings - Circuits, Devices and Systems, Vol.152, No.2, pp.183-188, Apr., 2005. https://doi.org/10.1049/ip-cds:20041110
  5. J.W. Sleight and R. Rios, "A continuous compact MOSFET model for fully and partially-depleted SOI devices", IEEE Transactions on Electron Devices, Vol.45, No.4, pp.821-825, Apr., 1998. https://doi.org/10.1109/16.662786
  6. S. Bolouki, M. Maddah, A. Afzali-Kusha, and M.E. Nokali, "A unified I-V model for PD/FD SOI MOSFETs with a compact model for floating body effects", Solid-State Electronics, Vol.47, No.11, pp.1909-1915, Nov., 2003. https://doi.org/10.1016/S0038-1101(03)00259-4
  7. J.P. Colinge, "Transconductance of SOI MOSFETs", IEEE Electron Device Letters, Vol.6, No.11, pp.573-574, Nov., 1985. https://doi.org/10.1109/EDL.1985.26234
  8. M. Lundstrom, "SOI Electrostatics: Lecture 25", Purdue University, West Lafayette 2008.
  9. P. Agarwal, G. Saraswat, and M.J. Kumar, "Compact Surface Potential Model for FD SOI MOSFET Considering Substrate Depletion Region", IEEE Transactions on Electron Devices, Vol.55, No.3, pp.789-795, Mar., 2008. https://doi.org/10.1109/TED.2007.914834
  10. R.V. Langevelde and F.M. Klaassen, "An explicit surface-potential-based MOSFET model for circuit simulation", Solid-State Electronics, Vol.44, No.3, pp.409-418, Dec., 2000. https://doi.org/10.1016/S0038-1101(99)00219-1
  11. Y.P. Tsividis, "Operation and Modeling of the MOS Transistor", 2nd edition, Oxford University Press, 2008.