참고문헌
- D. Ielmini et al, "Analysis of phase distribution in phase-change non-volatile memories," IEEE Electron Device Lett., Vol.25, No.7, pp.507-509, July, 2004. https://doi.org/10.1109/LED.2004.831219
- F. Bedeschi et al, "A bipolar-selected phase-change memory featuring multi-level cell storage," IEEE Journal of Solid-State Circuits, Vol.44, No.1, pp.217-227, Jan., 2009. https://doi.org/10.1109/JSSC.2008.2006439
- Y. Liao et al, "Phase change memory modeling using Verilog-A," Behavioral Modeling and Simulation Conf., pp.159-164, 2007.
- K. Kwong et al, "Verilog-A model for phase change memory simulation," Solid-State and Integrated- Circuit Tech. Conf., pp.492-495, 2008.
- Y. Liao et al, "Temperature-based phase change memory model for pulsing scheme assessment," IEEE Conf. Integrated Circuit Design and Tech., pp.199-202, 2008.
- K. Kwong et al, "Circuit implementation to describe the physical behavior of phase change memory," IEEE Conf. Electron Devices and Solid- State Circuits, pp.1-4, 2008.
- K. Jo et al, "A compact Verilog-A model for multilevel- cell phase-change rams," IEICE Electronics Express, Vol.6, No.19, pp.1414-1420, Oct., 2009. https://doi.org/10.1587/elex.6.1414
- D. Ventrice et al, "A phase change memory compact model for multilevel applications," IEEE Electron Device Lett., Vol.28, No.11, pp.973-975, Nov., 2007. https://doi.org/10.1109/LED.2007.907288
- X. Q. Wei et al, "HSPICE macromodel of pcram for binary and multilevel storage," IEEE Trans. Electron Devices, Vol.53, No.1, pp.56-62, Jan., 2006. https://doi.org/10.1109/TED.2005.860645
- C. M. Jung et al, "Continous ccurrent-voltage model of multi-level-cell phase-change rams using Verilog-A," in Proc. The 18th Korean Conf. on Semiconductors, pp.569-570, Feb., 2011.
- D. Batas and H. Fiedler, "A memristor SPICE implementation and a new approach for magnetic flux-controlled memristor modeling," IEEE Trans. Nanotechnology, Vol.10, No.2, pp.250-255, Mar., 2011 https://doi.org/10.1109/TNANO.2009.2038051
피인용 문헌
- PCRAM Flip-Flop Circuits with Sequential Sleep-in Control Scheme and Selective Write Latch vol.13, pp.1, 2013, https://doi.org/10.5573/JSTS.2013.13.1.058
- Behavioral Current-Voltage Model with Intermediate States for Unipolar Resistive Memories vol.13, pp.6, 2013, https://doi.org/10.5573/JSTS.2013.13.6.539
- Investigating Phase Transform Behavior in Indium Selenide Based RAM and Its Validation as a Memory Element vol.2016, pp.2314-4874, 2016, https://doi.org/10.1155/2016/6123268