DOI QR코드

DOI QR Code

FR4 PCB면적과 Via-hole이 LED패키지에 미치는 열적 특성 분석

Analysis of Thermal Properties in LED Package by Via-hole and Dimension of FR4 PCB

  • 김성현 (원광대학교 정보통신공학과) ;
  • 이세일 (원광대학교 정보통신공학과) ;
  • 양종경 (원광대학교 정보통신공학과) ;
  • 박대희 (원광대학교 정보통신공학과)
  • Kim, Sung-Hyun (Department of Information&Communication Engineering, Wonkwang University) ;
  • Lee, Se-Il (Department of Information&Communication Engineering, Wonkwang University) ;
  • Yang, Jong-Kyung (Department of Information&Communication Engineering, Wonkwang University) ;
  • Park, Dae-Hee (Department of Information&Communication Engineering, Wonkwang University)
  • 투고 : 2010.12.07
  • 심사 : 2011.01.28
  • 발행 : 2011.03.01

초록

In this study, the heat transfer capability have been improved by using via-holes in FR4 PCB, when the LED lighting is designed to solve the thermal problem. The thermal resistance and junction temperature were measured by changing the dimension of FR4 PCB and size of via hole. As a result, when the dimension was increased initially, the thermal resistance and junction temperature was decreased rapidly, the ones was stabilized after the dimension of 200 $[mm^2]$. Also, the light output was improved up to maximum 17% by formation of via-hole and expansion of dimension in FR4 PCB. Therefore, the thermal resistance and junction temperature could be improved by expansion of PCB dimension and configuration of via-hole ability.

키워드

참고문헌

  1. J. B. Kim, ELECTRONIC, 24, 6 (2009).
  2. Dimitar Georgiev Todorov, Lazar Georgiev Kapisazov, ETTRENDS (2008).
  3. J. Park, M. W. Shin, C. C. Lee, OPTICS LETTERS, 29, 2656 (2004). https://doi.org/10.1364/OL.29.002656
  4. S .L. Chuang, IEEE J. Quant. Electron, 33, 970 (1997). https://doi.org/10.1109/3.585485
  5. S .L .Chuang, IEEE J. Quant. Electron, 33, 970-979 (1997). https://doi.org/10.1109/3.585485
  6. X. Luo, W. Xiong, T. Cheng, S. Liu, Electronic Components and Technology Conference, 59th (2009).
  7. M. H. Shin, J. P. Kim, LED Introduction to Packaging Technology (Bookshill, 2009) p. 283.
  8. EIA/JESD51-1, http://www.jedec.org (1995).

피인용 문헌

  1. Anisotropic Wet-Etching Process of Si Substrate for Formation of Thermal Vias in High-Power LED Packages vol.19, pp.4, 2012, https://doi.org/10.6117/kmeps.2012.19.4.051
  2. Reflection Characteristics of Electroplated Deposits on LED Lead frame with Plating Condition vol.20, pp.2, 2013, https://doi.org/10.6117/kmeps.2013.20.2.029