• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1724-1725
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• 2011

본 논문에서는 LED 패키지의 방열문제를 해결하기 위해 FR4 PCB에 Via-hole을 형성함으로써 열전달 능력을 향상시키고자 하였다. 또한 FR4 PCB의 면적과 Via-hole 크기 및 수량을 변화를 주어 그에 따른 K-factor를 측정 하였으며 열 저항 특성을 분석하였다. 결과로서, Via-hole을 형성한 FR4 PCB의 경우 초기 면적이 증가함에 따라 열 저항 및 접합온도가 급격히 감소하는 특성을 보였으며 200 [mm2]에서 안정화 되는 특성을 보였다. 또한 PCB 면적 및 Via-hole을 형성함에 따라 광 출력이 최대 17% 향상 되었다. 따라서 접합온도 및 열 저항에 있어서 PCB면적의 증가 및 Via-hole을 구성함에 있어 열전달 능력을 향상시킬 수 있음을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.233-234
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• 2006

In this paper, Via hole pore were investigated during PLAS (PessureLess Assisted Constrained Sintering) process of LTCC. Ag and Ag-Pd paste mixture were tested for via paste. Ag paste with 10~25% Ag-Pd paste showed no via hole pore, but further increase of Ag-Pd contents in via paste increased via pore. From shrinkage curve, 10~25% Ag-Pd paste showed expansion behaviors before shrink and this phenomena result in the reduction of via hole pore during PLAS process.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.71-76
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• 2015

Recently, light emitting diodes (LEDs) have been studied to improve their efficiencies for the uses in various fields. Particularly in the aspect of chip structure, via hole type vertical LED chip is developed for improvement of light output power, and heat dissipations. However, current vertical type LEDs have still drawback, which is current concentration around the n-contact holes. In this research, to solve this phenomenon, we introduced isolation layer under n-contact electrodes. With this sub-electrode, even though the active area was decreased by about 2.7% compared with conventional via-hole type vertical LED, we could decrease the forward voltage by 0.2 V and wall-plug efficiency was improved approximately 4.2%. This is owing to uniform current flow through the area of n-contact.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.16-22
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• 1993

A via-hole process for reproducible and reliable GaAs MMIC fabrication is described. The via-hole etching process consists of two step dry etching. During the first etching step a BC $I_{3}$/C $I_{2}$/Ar gas mixure is used to achieve high etch rate and small lateral etching. In the second etching step. CC $L_{2}$ $F_{2}$ gas is used to achieve selective etching of the GaAs substrate with respect to the front side metal layer. Via holes are formed from the backside of a 100$\mu$m thick GaAs substrate that has been evaporated initially with 500.angs. thick chromium and subsequently a 2000.angs. thick gold layer. The fabricated via holes are electroplated with gold (~20$\mu$m thick) to form via connections. The results show that established via-hole process is satisfactory for GaAs MMIC fabrication.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.188-193
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• 2010

In this paper, SI(Signal Integrity) characteristic of the 4-layer PCB(Printed Circuit Boards) with a through-hole via was analyzed by impedance mismatching between the through-hole via and the transmission line, and deterioration of clock pulse response characteristic due to the P/G plane resonances which are generated between the power and the ground plane. The minimized impedance mismatching between the through-hole via and the transmission line for the improving of SI characteristic is confirmed by the TDR(Time Domain Reflector) simulation and lumped element modeling of the through-hole via. And the cancellation method of P/G plane resonances for improvement of the SI characteristic is represented by simulation result.

• Transactions of Materials Processing
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• v.13 no.1
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• pp.65-71
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• 2004

Recent electronic equipment becomes smaller, more functional, and more complex. According to these trends, LTCC(low temperature co-fired ceramic) has been emerged as a promising technology in packaging industry. It consists of multi-layer ceramic sheet, and the circuit has 3D structure. In this technology via hole formation plays an important role because it provides an electric path for the packaging interconnection network. Therefore via hole qualify is very important for ensuring performance of LTCC product. Via holes are formed on the green sheet that consists of ceramic(before sintering) layer and PET(polyethylene terephthalate) one. In this paper we found the correlation between hole quality and process condition such as PET thickness and ceramic thickness. The shear behavior of double layer sheet by micro hole punching which is different from that of single layer one was also discussed.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.160-163
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• 2002

Micro via hole Fabrication is studied by means of minimizing method to circuit size as many electric products developed to portable and minimize. Most of currently micro via hole fabrication using laser is that fabricate insulator layer using CO2 Laser after Cu layer by etching, or fabricate insulator layer using IR after trepanning Cu by UV. In this paper, it was performed that a metal layer and insulator layer were worked upon only one UV laser, and increase to processing speed by experiment.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.29-36
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• 2008

In this paper, mechanical reliability issues of copper through-wafer interconnections are investigated numerically and experimentally. A hermetic wafer level packaging for MEMS devices is developed. Au-Sn eutectic bonding technology is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of $1mm{\times}1mm{\times}700{\mu}m$. The robustness of the package is confirmed by several reliability tests. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, and copper diffusion phenomenon. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process. After implementing several improvements, reliability tests were performed, and via hole cracking as well as significant changes in the shear strength were not observed. Helium leak testing indicated that the leak rate of the package meets the requirements of MIL-STD-883F specification.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.3
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• pp.234-239
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• 2011

In this study, the heat transfer capability have been improved by using via-holes in FR4 PCB, when the LED lighting is designed to solve the thermal problem. The thermal resistance and junction temperature were measured by changing the dimension of FR4 PCB and size of via hole. As a result, when the dimension was increased initially, the thermal resistance and junction temperature was decreased rapidly, the ones was stabilized after the dimension of 200 $[mm^2]$. Also, the light output was improved up to maximum 17% by formation of via-hole and expansion of dimension in FR4 PCB. Therefore, the thermal resistance and junction temperature could be improved by expansion of PCB dimension and configuration of via-hole ability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.297-298
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• 2009

대부분의 반도체 소자의 고장 원인은 85%정도가 열로 인한 것이며, 고출력 LED는 인가된 에너지의 20%정도의 광으로 출력되며 나머지 80%가 열로 전환된다. 본 논문에서는 PMS-50과 KEITHLEY 2430을 이용하여 PCB 구조와 Via hole 구성에 따른 LED 패키지의 열적 광학적 특성을 분석하였다. 0.6mm의 Via hole을 가진 FR4 PCB의 열특성이 가장 우수하였으며, Via hole 0.6mm FR4 PCB의 경우 McPCB에 상응하는 광출력 특성을 보였다.