The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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A Modified Sum-Product Algorithm for Error Floor Reduction in LDPC Codes

저밀도 패리티 검사부호에서 오류마루 감소를 위한 수정 합-곱 알고리즘

  • 유석근 (경북대학교 IT대학 전자공학부) ;
  • 강석근 (경상대학교 전기전자공학부) ;
  • 주언경 (경북대학교 IT대학 전자공학부)
  • Received : 2010.01.06
  • Accepted : 2010.04.27
  • Published : 2010.05.31
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Abstract

In this paper, a modified sum-product algorithm to correct bit errors captured within the trapping sets, which are produced in decoding of low-density parity-check (LDPC) codes, is proposed. Unlike the original sum-product algorithm, the proposed decoding method consists of two stages. Whether the main cause of decoding failure is the trapping sets or not is determined at the first stage. And the bit errors within the trapping sets are corrected at the second stage. In the modified algorithm, the set of failed check nodes and the transition patterns of hard-decision bits are exploited to search variable nodes in the trapping sets. After inverting information of the variable nodes, the sum-product algorithm is carried out to correct the bit errors. As a result of simulation, the proposed algorithm shows continuously improved error performance with increase in the signal-to-noise ratio. It is, therefore, considered that the modified sum-product algorithm significantly reduces or possibly eliminates the error floor in LDPC codes.

본 논문에서는 저밀도 패리티 검사부호의 복호에서 발생하는 트랩핑 세트에 갇힌 오류를 정정할 수 있는 수정 합-곱 알고리즘을 제안한다. 원래 합-곱 알고리즘과는 달리 제안된 방법은 반복복호의 실패 원인이 트랩핑 세트인지를 판단하는 과정과 트랩핑 세트에 갇힌 오류를 정정하는 2단계 복호과정으로 구성된다. 수정 합-곱 알고리즘에서는 트랩핑 세트에 포함된 변수노드를 검색하기 위하여 실패 검사노드 집합과 경판정 비트들의 천이패턴을 이용한다. 그리고 검색된 변수노드의 정보를 반전시킨 다음 합-곱 알고리즘을 수행함으로써 트랩핑 세트에 갇힌 오류를 정정한다. 모의실험 결과 제안된 복호알고리즘은 신호 대 잡음비의 증가에 따라 지속적으로 향상되는 오류성능을 보인다. 따라서 수정 합-곱 알고리즘은 저밀도 패리티 검사부호에서 발생하는 오류마루 현상을 현저히 감소시키거나 거의 제거할 수 있는 것으로 사료된다.

Keywords

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