대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Offset Self-Calibration 기법을 적용한 1.2V 7-bit 800MSPS Folding-Interpolation A/D 변환기의 설계

Design of a 1.2V 7-bit 800MSPS Folding-Interpolation A/D Converter with Offset Self-Calibration

  • 김대윤 (동국대학교-서울 반도체과학과) ;
  • 문준호 (동국대학교 서울 반도체과학과) ;
  • 송민규 (동국대학교 서울 반도체과학과)
  • Kim, Dae-Yun (Department of Semiconductor Science, Dongguk Univ-Seoul) ;
  • Moon, Jun-Ho (Department of Semiconductor Science, Dongguk Univ-Seoul) ;
  • Song, Min-Kyu (Department of Semiconductor Science, Dongguk Univ-Seoul)
  • 발행 : 2010.03.25
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초록

본 논문에서는 offset self-calibration 기법을 적용한 7-bit 1GSPS folding-interpolation A/D 변환기를 제안한다. 제안하는 A/D 변환기는 folding rate 2, interpolation rate 8의 1+6 구조로 고속 동작에 적합하게 설계되었다. 또한 offset self-calibration 회로를 설계하여 공정 mismatch, 기생 저항, 기생 캐패시턴스 등에 의한 offset-voltage의 변화를 감소시켜 A/D 변환기의 성능 특성을 향상 시켰다. 제안하는 A/D 변환기는 1.2V 65nm 1-poly 6-metal CMOS 공정을 사용하여 설계 되었으며 유효 칩 면적은 $0.87mm^2$, 1.2V 전원전압에서 약 110mW의 전력소모를 나타내었다. 측정 결과 샘플링 주파수 800MHz, 입력 주파수 250MHz에서 39.1dB의 SNDR 특성을 보여주었으며, offset self-calibration 회로를 사용 하지 않은 A/D 변환기에 비해 SNDR이 약 3 dB 향상되었다.

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

키워드

참고문헌

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