Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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High Frame Rate CMOS Image Sensor with Column-wise Cyclic ADC

컬럼 레벨 싸이클릭 아날로그-디지털 변환기를 사용한 고속 프레임 레이트 씨모스 이미지 센서

  • Lim, Seung-Hyun (Department of Electrical and Electronic Eng., Yonsei University) ;
  • Cheon, Ji-Min (Department of Electrical and Electronic Eng., Yonsei University) ;
  • Lee, Dong-Myung (Department of Electrical and Electronic Eng., Yonsei University) ;
  • Chae, Young-Cheol (Department of Electrical and Electronic Eng., Yonsei University) ;
  • Chang, Eun-Soo (Department of Electrical and Electronic Eng., Yonsei University) ;
  • Han, Gun-Hee (Department of Electrical and Electronic Eng., Yonsei University)
  • 임승현 (연세대학교 전기전자공학과) ;
  • 천지민 (연세대학교 전기전자공학과) ;
  • 이동명 (연세대학교 전기전자공학과) ;
  • 채영철 (연세대학교 전기전자공학과) ;
  • 장은수 (연세대학교 전기전자공학과) ;
  • 한건희 (연세대학교 전기전자공학과)
  • Published : 2010.01.25
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Abstract

This paper proposes a high-resolution and high-frame rate CMOS image sensor with column-wise cyclic ADC. The proposed ADC uses the sharing techniques of OTAs and capacitors for low-power consumption and small silicon area. The proposed ADC was verified implementing the prototype chip as QVGA image sensor. The measured maximum frame rate is 120 fps, and the power consumption is 130 mW. The power supply is 3.3 V, and the die size is $4.8\;mm\;{\times}\;3.5\;mm$. The prototype chip was fabricated in a 2-poly 3-metal $0.35-{\mu}m$ CMOS process.

본 논문에서는 고해상도 및 고속 카메라용 column-wise Cyclic ADC 기반의 이미지 센서를 제안한다. 제안된 센서는 면적 및 전력 소모를 최소화 하기 위해 내부 블록에 사용되는 operational transconductance amplifier (OTA) 및 capacitor를 공유하는 기법을 사용하였다. 제안된 ADC는 QVGA급 화소의 이미지 센서로 프로토타입 칩을 제작하여 검증되었다. 측정결과, 최대 프레임 레이트는 120 fps 이며, 전력소모는 130 mW 이다. 전원 전압은 3.3 V가 공급되었고, 프로토타입은 $4.8\;mm\;{\times}\;3.5\;mm$의 실리콘 면적을 차지한다.

Keywords

References

  1. A. Gerosa, A. Maniero, and A. Neviani, 'A fully integrated two-channel A/D interface for the acquisition of cardiac signals in implantable pacemakers,' IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1083-1093, July 2004 https://doi.org/10.1109/JSSC.2004.829921
  2. L. S. Y. Wong, S. Hossain, A. Ta, J. Edvinsson, H. H. Rivas, and H. Naas, 'A Very Low-Power CMOS Mixed-Signal IC for Implantable Pacemaker Applications,' IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2446-2456, Dec. 2004 https://doi.org/10.1109/JSSC.2004.837027
  3. A. Bashirotto, D. Bijno, R. Castello, and F. Montecchi, 'A 1V $1.2{\mu}W$ 4th order bandpass switched-opamp SC filter for a cardiac pacer sensing stage,' in Proc. ISCAS, Geneva, May 2000, vol. 3, pp. 173-176
  4. A. E. Zadeh, 'Nano-power switched-capacitor bandpass filters for medical implantable pacemakers and defibrillators,' in Proc MWSCAS, Aug. 2008, pp. 29-32
  5. S. Decker, R. D. McGrath, K. Brehmer, and C. G. Sodini, 'A 256 ' 256 CMOS Imaging Array with Wide Dynamic Range Pixels and Column-Parallel Digital Output,' IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2081-2091, Dec. 1998 https://doi.org/10.1109/4.735551
  6. M. Mase, S. Kawahito, M. Sasaki, Y. Wakamori, and M. Furuta, 'A Wide Dynamic Range CMOS Image Sensor With Multiple Exposure-Time Signal Outputs and 12-bit Column-Parallel Cyclic A/D Converters,' IEEE J.Solid-State Circuits, vol. 40, no. 12, pp. 2787-2795, Dec. 2005 https://doi.org/10.1109/JSSC.2005.858477
  7. M. Furuta, Y. Nishikawa, T. Inoue, and S. Kawahito, 'A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters,' IEEE J. Solid-State Circuits, vol .42, no. 4, pp. 766-774, Apr .2007 https://doi.org/10.1109/JSSC.2007.891655
  8. S. Kawahito, J. Park, K. Isobe, S. Shafie, T. Iida, and T. Mizota, 'A CMOS Image Sensor Integrating Column-Parallel Cyclic ADCs with On-Chip Digital Error Correction Circuits,' in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 56-595