Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Optimum Design of Junctionless MOSFET Based on Silicon Nanowire Structure and Analysis on Basic RF Characteristics

실리콘 나노 와이어 기반의 무접합 MOSFET의 최적 설계 및 기본적인 고주파 특성 분석

  • Cha, Seong-Jae (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Kim, Kyung-Rok (School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology) ;
  • Park, Byung-Gook (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Rang, In-Man (School of Electronics Engineering, Kyungpook National University)
  • 조성재 (서울대학교 전기.컴퓨터공학부) ;
  • 김경록 (울산과학기술대학교 전기전자컴퓨터) ;
  • 박병국 (서울대학교 전기.컴퓨터공학부) ;
  • 강인만 (경북대학교 전자공학부)
  • Received : 2010.08.02
  • Accepted : 2010.09.25
  • Published : 2010.10.25
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Abstract

The source/channel/drain regions are formed by ion implantation with different dopant types of $n^+/p^{(+)}/n^+$ in the fabrication of the conventional n-type metal-oxide-semiconductor field effect transistor(NMOSFET). In implementing the ultra-small devices with channel length of sub-30 nm, in order to achieve the designed effective channel length accurately, low thermal budget should be considered in the fabrication processes for minimizing the lateral diffusion of dopants although the implanted ions should be activated as completely as possible for higher on-current level. Junctionless (JL) MOSFETs fully capable of the the conventional NMOSFET operations without p-type channel for enlarging the process margin are under researches. In this paper, the optimum design of the JL MOSFET based on silicon nanowire (SNW) structure is carried out by 3-D device simulation and the basic radio frequency (RF) characteristics such as conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) for the optimized device. The channel length was 30 run and the design variables were the channel doping concentration and SNW radius. For the optimally designed JL SNW NMOSFET, $f_T$ and $f_{max}$ high as 367.5 GHz and 602.5 GHz could be obtained, respectively, at the operating bias condition $V_{GS}$ = $V_{DS}$ = 1.0 V).

기존의 n-type metal-oxide-semiconductor field effect transistor(NMOSFET)은 $n^+/p^{(+)}/n^+$ type의 이온 주입을 통하여 소스/채널/드레인 영역을 형성하게 된다. 30 nm 이하의 채널 길이를 갖는 초미세 소자를 제작함에 있어서 설계한 유효 채널 길이를 정확하게 얻기 위해서는 주입된 이온들을 완전히 activation하여 전류 수준을 향상시키면서도 diffusion을 최소화하기 위해 낮은 thermal budget을 갖도록 공정을 설계해야 한다. 실제 공정에서의 process margin을 완화할 수 있도록 오히려 p-type 채널을 형성하져 않으면서도 기존의 NMOSFET의 동작을 온전히 구현할 수 있는 junctionless(JL) MOSFET이 연구중이다. 본 논문에서는 3차원 소자 시뮬레이션을 통하여 silicon nanowire(SNW) 구조에 접목시킨 JL MOSFET을 최적 설계하고 그러한 조건의 소자에 대하여 conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) 등의 기본적인 고주파 특성을 분석한다. 채널 길이는 30 nm이며 설계 변수는 채널 도핑 농도와 채널 SNW의 반지름이다. 최적 설계된 JL SNW NMOSFET에 대하여 동작 조건($V_{GS}$ = $V_{DS}$ = 1.0 V)에서 각각 367.5 GHz, 602.5 GHz의 $f_T$, $f_{max}$를 얻을 수 있었다.

Keywords

References

  1. H. Xiao, Introduction to Semiconductor Manufacturing Technology, Prentice Hall, pp. 150-157, 2001.
  2. C.-W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J.-P. Colinge, "High-Temperature Performance of Silicon Junctionless MOSFETs," IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 620-625, Mar. 2010. https://doi.org/10.1109/TED.2009.2039093
  3. C.-W. Lee, A. N. Nazarov, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, R. T. Doria, and J.-P. Colinge, "Low Subthreshold Slope in Junctioless Multigate Transistors," Appl. Phys. Lett., vol. 96, no. 10, p. 102106, Mar. 2010.
  4. J.-P. Colinge, C.-W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A. N. Nazalov, R. T. Doria, "Reduced Electric Field in Junctionless Transistors," Appl. Phys. Lett., vol. 96, no. 7, p. 073510, Feb. 2010. https://doi.org/10.1063/1.3299014
  5. S. Hamedi-Hagh and A. Bindal, "Spice Modeling of Silicon Nanowire Field-Effect Transistors for High-Speed Analog Integrated Circuits", IEEE Trans. Nanotechnol., vol. 7, no. 6, pp. 766-775, Nov. 2008. https://doi.org/10.1109/TNANO.2008.2004409
  6. J. Song, B. Yu, Y. Yuan, and Y, Taur, "A Review on Compact Modeling of Multiple-Gate MOSFETs," IEEE Trans. Circuits Syst. Regul. Pap., vol.56, no. 8, pp. 1858-1869, Aug. 2009.
  7. 유윤섭, 김한정, "공핍모드 N형 나노선 전계효과 트랜지스터의 전류 전도 모델," 전자공학회논문지-SD, 제45권, 제4호, 49-56쪽, 2008년 4월
  8. International Technology Roadmap for Semiconductors (ITRS), 2009 edition, available at http://www.itrs.net/Links/2009ITRS/Home2009.htm
  9. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, pp. 158-159, 1998.
  10. S. M. Sze and K. K. Ng, Physics of Semiconductor Devices (3rd edition), Wiely-Interscience, pp. 314-316, 2007.
  11. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, pp. 153-154, 1998.
  12. J. Kim, J. Lee, Y. Kwon, B.-G. Park, J. D. Lee, and H. Shin, "Extraction of Ballistic Parameters in 65 nm MOSFETs," J. Semicond. Technol. Sci., vol. 9, no. 1, pp. 55-60, Mar. 2009. https://doi.org/10.5573/JSTS.2009.9.1.055
  13. 김지현, 손애리, 정나래, 신형순, "이차원 양자 효과를 고려한 극미세 Double-Gate MOSFET 특성 분석," 대한전자공학회논문지, 제45권 SD편, 제10호, 15-22쪽, 2008년 10월.
  14. Y. Tsividis, Operation and Modeling of the MOS Transistor (2nd edition), Oxford University Press, pp. 501-503, 1999.
  15. 차지용, 차준영, 정대현, 이성현, "MOSFET의 RF성능 최적화를 위한 단위 게이트 Finger 폭에 대한 $f_T$ 및 $f_{max의}$ 종속데이터 분석," 대한전자공학회 논문지, 제45권 SD편, 제9호, 22-25쪽, 2008년 9월.
  16. S. Cho, H.-S. Jhon, J. H. Lee, S. H. Park, H. Shin, and B.-G. Park, "Device and Circuit Codesign Strategy for Application to Low-Noise Amplifier Based on Silicon Nanowire Metal- Oxide-Semiconductor Field Effect Transistors," Jpn. J. Appl. Phys., Part I, vol. 49, no. 4, pp. 4031-4037, Apr. 2010.