JSTS:Journal of Semiconductor Technology and Science

  • 제10권3호
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  • Pages.193-202
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  • 2010
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm and Its Folded Architecture

  • Park, Jeong-In (Dep. of Information and Communication Eng., Inha University) ;
  • Lee, Ki-Hoon (Dep. of Information and Communication Eng., Inha University) ;
  • Choi, Chang-Seok (Dep. of Information and Communication Eng., Inha University) ;
  • Lee, Han-Ho (Dep. of Information and Communication Eng., Inha University)
  • 투고 : 2010.06.28
  • 심사 : 2010.08.25
  • 발행 : 2010.09.30
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초록

This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

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참고문헌

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  3. Low Complexity Reed-Solomon Decoder Design with Pipelined Recursive Euclidean Algorithm vol.E99.A, pp.12, 2016, https://doi.org/10.1587/transfun.E99.A.2453
  4. FPGA based area efficient RS(23, 17) codec vol.23, pp.3, 2017, https://doi.org/10.1007/s00542-016-3058-1