ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
권호 표지

A Novel BIRA Method with High Repair Efficiency and Small Hardware Overhead

  • Yang, Myung-Hoon (Department of Electrical & Electronic Engineering, Yonsei University) ;
  • Cho, Hyung-Jun (Department of Electrical & Electronic Engineering, Yonsei University) ;
  • Jeong, Woo-Sik (Department of Electrical & Electronic Engineering, Yonsei University) ;
  • Kang, Sung-Ho (Department of Electrical & Electronic Engineering, Yonsei University)
  • Received : 2009.01.15
  • Accepted : 2009.04.13
  • Published : 2009.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.

Keywords

References

  1. R.P. Cenker et al., “A Fault-Tolerant 64K Dynamic Random-Access Memory,” IEEE Trans. Electron Devices, vol. 26, no. 6, June 1979, pp. 853-860. https://doi.org/10.1109/T-ED.1979.19509
  2. J.R. Day, “A Fault-Driven Comprehensive Redundancy Algorithms,” Proc. Int'l Test Conf., 1985, pp. 35-44.
  3. S.-Y. Kuo and W.K. Fuchs, “Efficient Spare Allocation in Reconfigurable Arrays,” IEEE Design and Test, vol. 4, no. 1, Feb. 1987, pp. 24-31.
  4. T. Kawagoe et al., “A Built-in Self-Analyzer (CRESTA) for Embedded DRAMs,” Proc. Int'l Test Conf., 2000, pp. 567-574.
  5. S. Shoukourian, V. Vardanian, and Y. Zorian, “An Approach for Evaluation of Redundancy Analysis Algorithm,” Proc. IEEE Memory Technology, Design and Testing Workshop, 2001, pp. 51-55.
  6. C.-T. Huang, C.-F. Wu, and C.-W. Wu, “Built-in Redundancy Analysis for Memory Yield Improvement,” IEEE Trans. Reliability, vol. 52, no. 4, Dec. 2003, pp. 386-399. https://doi.org/10.1109/TR.2003.821925
  7. P. Ohler, S. Hellebrand, and H.-J. Wunderlich, “An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy,” Proc. IEEE European Test Symp., 2007, pp. 91-96.