Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Tunneling Properties in High-k Insulators with Engineered Tunnel Barrier for Nonvolatile Memory

차세대 비휘발성 메모리에 사용되는 High-k 절연막의 터널링 특성

  • 오세만 (광운대학교 전자재료공학과) ;
  • 정명호 (광운대학교 전자재료공학과) ;
  • 박군호 (광운대학교 전자재료공학과) ;
  • 김관수 (광운대학교 전자재료공학과) ;
  • 정홍배 (광운대학교 전자재료공학과) ;
  • 이영희 (광운대학교 전자재료공학과) ;
  • 조원주 (광운대학교 전자재료공학과)
  • Published : 2009.06.01
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Abstract

The metal-insulator-silicon (MIS) capacitors with $SiO_2$ and high-k dielectrics ($HfO_2$, $Al_2O_3$) were fabricated, and the current-voltage characteristics were investigated. Especially, an effective barrier height between metal gate and dielectric was extracted by using Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot of quantum mechanical(QM) modeling. The calculated barrier heights of thermal $SiO_2$, ALD $SiO_2$, $HfO_2$ and $Al_2O_3$ are 3.35 eV, 0.6 eV, 1.75 eV, and 2.65 eV, respectively. Therefore, the performance of non-volatile memory devices can be improved by using engineered tunnel barrier which is considered effective barrier height of high-k materials.

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References

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