JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Comparison of Circuit Reduction Techniques for Power Network Noise Analysis

  • Kim, Jin-Wook (Dep. ECE., Pohang University of Science and Technology) ;
  • Kim, Young-Hwan (Dep. ECE., Pohang University of Science and Technology)
  • Received : 2009.08.23
  • Published : 2009.12.30
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Abstract

The endless scaling down of the semiconductor process made the impact of the power network noise on the performance of the state-of-the-art chip a serious design problem. This paper compares the performances of two popular circuit reduction approaches used to improve the efficiency of power network noise analysis: moment matching-based model order reduction (MOR) and node elimination-based MOR. As the benchmarks, we chose PRIMA and R2Power as the matching-based MOR and the node elimination-based MOR. Experimental results indicate that the accuracy, efficiency, and memory requirement of both methods very strongly depend on the structure of the given circuit, i.e., numbers of the nodes and sources, and the number of moments to preserve for PRIMA. PRIMA has higher accuracy in general, while the error of R2Power is also in the acceptable range. On the other hand, PRIMA has the higher efficiency than R2Power, only when the numbers of nodes and sources are small enough. Otherwise, R2Power clearly outperforms PRIMA in efficiency. In the memory requirement, the memory size of PRIMA increases very quickly as the numbers of nodes, sources, and preserved moments increase.

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