대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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MIMO-OFDM 시스템을 위한 고속 저면적 128/64-point $Radix-2^4$ FFT 프로세서 설계

A High-Speed Low-Complexity 128/64-point $Radix-2^4$ FFT Processor for MIMO-OFDM Systems

  • 리우 항 (인하대학교 정보통신공학부) ;
  • 이한호 (인하대학교 정보통신공학부)
  • Hang, Liu (Dept. of Information and Communication Engineering, Inha University) ;
  • Lee, Han-Ho (Dept. of Information and Communication Engineering, Inha University)
  • 발행 : 2009.02.25
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초록

본 논문은 높은 데이터 처리율을 요하는 MIMO-OFDM 시스템을 위하여 고속의 낮은 하드웨어 복잡도를 가진 128/64-point $radix-2^4$ FFT/IFFT 프로세서 설계에 대해 제안한다. 높은 Radix 다중경로 지연 피드백 (MDF) FFT구조는 고속의 데이터 처리율과 낮은 하드웨어 복잡도를 제공한다. 제안하는 프로세서는 128-point와 64 Point FFT/IFFT의 동작을 지원할 뿐만 아니라 4-병렬 데이터 경로를 사용함으로써 높은 데이터 처리율을 지원한다. 또한, 제안하는 프로세서는 기존의 128/64-point FFT/IFFT 프로세서에 비해 낮은 하드웨어 복잡도를 지닌다. 제안된 FFT/IFFT 프로세서는 IEEE 802.11n 표준의 요구사항을 만족시키며 140MHz 클락 속도에서 560MSample/s의 높은 데이터 처리율을 가진다.

This paper presents a novel high-speed, low-complexity flexible 128/64-point $radix-2^4$ FFT/IFFT processor for the applications in high-throughput MIMO-OFDM systems. The high radix multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme. The proposed processor not only supports the operation of FFT/IFFT in 128-point and 64-point but can also provide a high data processing rate by using a four-parallel data-path scheme. Furthermore, the proposed design has a less hardware complexity compared with traditional 128/64-point FFT/IFFT processors. Our proposed processor has a high throughput rate of up to 560Msample/s at 140MHz while requiring much smaller hardware expenditure satisfying IEEE 802.11n standard requirements.

키워드

참고문헌

  1. J A C. Bingham, 'Multicarrier modulation for data transmission: an idea whose time has come,' IEEE Commun. Mag., vol. 28, no. 5, pp. 5-14, May 1990 https://doi.org/10.1109/35.54342
  2. Y -W. Lin, and C - Y. Lee, 'Design of an FIT/IFFf processor for MlMO OFDM systems,' IEEE Transactions on Circuits and Systems, vol. 54, no. 4, pp. 807-815, April 2007 https://doi.org/10.1109/TCSI.2006.888664
  3. G. L. Stuber, J R. Barry, S. W. McLaughlin, Y. Li, M.A. Ingram, and T.R Pratt, 'Broadband MlMO-OFDM wireless communications', Proc. IEEE, 92, (2), pp. 271 - 294, 2004 https://doi.org/10.1109/JPROC.2003.821912
  4. D. Borkowski, and L. Bruhl, 'Optimized hardware architecture for real-time equalization in single and multi-carrier MlMO systems', 3rd Workshop on Software Radio, Karlsruhe, Germany, 2004
  5. J Lee and R Lee, 'A High-Speed 2-Parallel Radix-t FFT/IFFf Processor for MB-OFDM UWB Systems,' IEICE Trans. on Fundamentals of Electronics, communications, and Computer Science, vol. E91-A, no. 4, pp. 1206-1211, April 2008
  6. S-M. Kim, J-G. Chung, and K K Parhi, 'Low Error Fixed-width CSD Multiplier with Efficient Sign Extension,' IEEE Trans. on Circuits and Systems-II, vol. 50, no. 12, December 2003 https://doi.org/10.1109/TCSII.2003.820231
  7. W-c. Yeh and C-W. Jen, 'High-speed and low-power split-radix FFT,' IEEE Trans. Acoust., Speech, Signal Process., vol. 51, no. 3, pp.864 - 874, March 2003
  8. L. Dadda, 'On Parallel Digital Multipliers,' Alta Frequenza 45:574-580, 1976
  9. K J Cho, K C. Lee, J G. Chung, and K K Parhi, 'Design of Low-error. Fixed-width Modified Booth Multiplier,' IEEE Trans. Very Large Scale. Integr. (VLSI), vo1.12, no.5, pp.522- 531, May 2004 https://doi.org/10.1109/TVLSI.2004.825853
  10. L. Liu, J Ren, X. Wang, F. Ye, 'Design of Low-power, IGS/s Throughput FFT for MlMO-OFDM UWB Communication System,' IEEE International Symposium on Circuits and Systems, vol.2, no.25, pp.2594 - 2597, May 2007