전자공학회논문지 IE

대한전자공학회 (The Institute of Electronics and Information Engineers)
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코드 기반 기법을 이용한 디지털 회로의 스캔 테스트 데이터와 전력단축

Reduction of Test Data and Power in Scan Testing for Digital Circuits using the Code-based Technique

  • 허용민 (동서울대학 컴퓨터소프트웨어과) ;
  • 신재흥 (동서울대학 디지털방송미디어과)
  • Hur, Yong-Min (Dept. of Computer Software, Dong Seoul College) ;
  • Shin, Jae-Heung (Dept. of Digital Broadcasting & Media, Dong Seoul College)
  • 발행 : 2008.09.25
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초록

디지털 논리회로의 테스트 데이터와 전력소비를 단축시킬 수 있는 효율적인 테스트 방법을 제안한다. 제안 하는 테스트 방법은 테스트장비내의 테스트 데이터 저장 공간을 줄이는 하이브리드 run-length 인코딩 벙법에 기초하고, 수정된 Bus-invert 코딩 방법과 스캔 셀 설계를 제안하여, 스캔 동작시의 개선된 전력 단축효과를 가져온다. ISCAS'89 벤치마크 회로의 실험결과 고장 검출율의 저하 없이 평균 전력은 96.7%, 피크전력은 84%의 단축을 보이며 테스트 데이터는 기존 방법보다 78.2%의 압축을 갖는다.

We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

키워드

참고문헌

  1. L. Whetsel, "Adapting scan architecture for low power operation," in Proceedings of the International Test Conference, pp. 863-872, Atlantic, Oct., 2000
  2. P. Rosinger, P. T. Gonciari, B. M. Al-Hashimi, and N. Nicolici, "Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip," IEE Electronic letters, 37, pp. 1434-1436, 2001 https://doi.org/10.1049/el:20010981
  3. Xiaodong Chen and Michael S. Hsiao, "Energy-efficient logic BIST based on state correlation analysis," in Proceedings of VLSI Test Symposium, pp. 267-272, Napa Valley, May, 2003
  4. R. Sankaralingam, R. R. Oruganti and N. A. Touba, "Static compaction techniques to control scan vector power dissipation," in Proceedings of VLSI Test Symposium, pp. 35-40, Montreal, May, 2000
  5. A. Chandra and K. Chakrabarty, "Combining low-power scan testing and test data compression for system-on-a-chip," in Proceedings of IEEE/ACM Design Automation Conference, pp. 166-169, Las Vegas, June, 2001
  6. Il-soo Lee, Yong Min Hur, and Tony Ambler, "The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time," 13th Asian Test Symposium, pp. 94-97, 2004
  7. Yongmin Hur, "Compression of test data for SOCs using a modified run-length method," in IEEE International Test Synthesis Workshop, Santa barbara, Apr. 2003
  8. A. Chandra and K. Chakrabarty, "Test data compression for system-on-a-chip using Golomb codes," in Proceedings of VLSI Test Symposium, pp. 113-120, Montreal, Apr., 2000
  9. A. Chandra and K. Chakrabarty, "Frequency- directed run-length(FDR) codes with application to system-on-a-chip test data compression," in Proceedings of VLSI Test Symposium, pp 42-47, Marina Del Rey, Mar., 2001
  10. A. Jas, J. Ghosh Dastidar, and N. Touba, "Scan vector compression/decompression using statistical coding," in Proceedings of VLSI Test Symposium, pp. 114-121, San Diego, Apr, 1999
  11. Mircea R. Stain and Wayne P. Burleson, "Bus-invert coding for low-power I/O," IEEE Trans. VLSI Systems, 3, pp. 49-58, 1995 https://doi.org/10.1109/92.365453
  12. I. Hamazaoglu and J. H. Patel, "Test set compaction algorithms for combinational circuits," in Proceedings of International Conference on CAD, pp. 283-289, San Jose, Nov., 1998
  13. P. T. Gonciari, B. M. Al-Hashimi, and N. Nicolici, "Improving compression ratio, area overhead, and test application time for system- on-a-chip test data compression/decompression," in Design, Automation and Test in Europe Conference, pp. 604-611, Paris, Mar., 2002