참고문헌
- Y. J. Ahn, B. J. Cho, H. S. Kang, C.-H. Lee, C. Lee, J.-M. Yoon, T. Y. Kim, E. S. Cho, S.-K. Sung, D. G. Park, K. N. Kim, and B.-I. Ryu, "Test structure for performance evaluation of 3 dimensional FinFET", Proc. IEEE 2005 Int. Conf. on Microelectronic test structures, Vol. 18, 2005
- S.-K. Sung, S.-H. Lee, B. Y. Choi, J. J. Lee, J.-D. Choe, E. S. Cho, Y. J. Ahn, D. U. Choi, C.-H. Lee, D. H. Kim, Y.-S. Lee, S. B. Kim, D. G. Park, and B.-I. Ryu, "SONOStype FinFET Device using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory", in VLSI Symp. Tech. Dig., p. 86, 2006
- C. Y. Lin, C. Y. Chang, and C. Hsu, "Suppression of boron penetration in BF2- implanted p-type gate MOSFET by trapping of fluorine in amorphous gate", IEEE Trans. Electron Devices, Vol. 42, No. 8, p. 1503, 1995 https://doi.org/10.1109/16.398666
- C. M. Maritan, L. P. Berndt, N. G. Tarr, J. M. Bullerwell, and G. M. Jenkins, "Poly silicon emitter p-n-p transistors", IEEE Trans. on Electron Devices, Vol. 36. No. 6, 1989
- M. Boukezzata, B. Birouk, F. Mansour, and D. B. Daspet, "Second-oxidation properties of thin polysilicon films grown by LPCVD and heavily in situ boron-doped", Thin Solid Films, Vol. 335, No. 1-2, p. 70, 1998 https://doi.org/10.1016/S0040-6090(98)00894-3
- B. Caussat, E. Scheid, B. de Mauduit, and R. Berjoan, "Influence of dopant concentration and type of substrate on the local organization of low-pressure chemical vapour deposition in situ boron doped silicon films from silane and boron trichloride", Thin Solid Films, Vol. 446, No. 2, p. 218, 2004 https://doi.org/10.1016/j.tsf.2003.10.010
- J. Y. C. Sun, C. Wong, Y. Taur, and C. H. Hsu, "Study of boron penetration through thin oxide with p+-polysilicon gate", Symp on VLSI Technol Tech Dig., p. 17, 1989
- J. R. Pfiester, F. K. Baker, T. C. Mele, H.-H. Tseng, P. J. Tobin, J. D. Hayden, J. W. Miller, C. D. Gunderson, and L. C. Parrillo, "The effects of boron penetration on p+ polysilicon gates PMOS devices", IEEE Trans. Electron Devices, Vol. 37, p. 1842, 1990 https://doi.org/10.1109/16.57135
- Y. Okazaki, S. Nakayama, M. Miyake, and T. Kobayashi, "Characteristics of Sub- 1/4-pm gate surface channel PMOSFET's using a multilayer gate structure of borondoped poly-Si on thin nitrogen-doped poly- Si", IEEE Trans. on Electron Devices, Vol. 41, No. 12, 1994