Effective Motion Compensation Method of H.264 on Multimedia Mobile System

멀티미디어 모바일 시스템에서의 효율적인 H.264 움직임 보간법

  • 정대영 (연세대학교 컴퓨터과학과) ;
  • 지신행 (연세대학교 컴퓨터과학과) ;
  • 박정욱 (연세대학교 컴퓨터과학과) ;
  • 김신덕 (연세대학교 컴퓨터과학과)
  • Published : 2007.10.15

Abstract

Power-aware design is one of the most important areas to be emphasized in multimedia mobile systems, in which data transfers dominate the power consumption. In this paper, we propose a new architecture for motion compensation (MC) of H.264/AVC with power reduction by decreasing the data transfers. For this purpose, a reconfigurable microarchitecture based on data type is proposed for interpolation and it is mapped onto the dedicated motion compensation IP (intellectual property) effectively without sacrificing the performance or the system latency. The original quarter-pel interpolation equation that consists of one or two half-pel interpolations and one averaging operation is designed to have different execution control modes, which result in decreasing memory accesses greatly and maintaining the system efficiency. The simulation result shows that the proposed method could reduce up to 87% of power consumption caused by data transfers over the conventional method in MC module.

데이타 전송이 전력 소비 중 가장 많은 부분을 차지하는 멀티미디어 모바일 시스템에서 전력감지 설계는 가장 중요한 분야 중 하나이다. 이 논문에서는 H.264/AVC의 MC(움직임 보정)에서 데이터 전송을 감소시킴으로써 전력 소비를 줄이는 새로운 구조를 제안한다. 이러한 목적으로 성능 저하 혹은 시스템의 지연 없이 MC(Motion Compensation) IP(Intellectual Property)에 효과적으로 접목되는 재구성 가능한 마이크로 아키텍처를 제안한다. 하나 또는 두 1/2 보간법과 한 평균법으로 이루어진 이전 1/4 보간법 공식은 메모리 접근을 줄이고 시스템 효율성을 유지하는 다른 수행 제어 형식을 가지도록 새로이 설계되었다. 모의 시험의 결과로써, MC 모듈에서 이전 방법을 사용했을 때 데이타 전송으로 인해 일어나는 전력 소모의 87%가 제안된 방법을 이용해서 줄어든 것을 보여준다.

Keywords

References

  1. Vahid, F., Givargis T.: Platform Tuning for Embedded Systems Design. Computer, Vol. 34 N. 3, Mar. (2001) 112-114 https://doi.org/10.1109/2.901171
  2. Smith, R., Fant, K., Parker, D., Stephani, R., Ching-Yi, W.: System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach. Processing of Journal of VLSI Signal, 18 (1998) 89-109 https://doi.org/10.1023/A:1008011223920
  3. Kakerow, R.: Low Power Design Methodologies for Mobile Communication Computer Design. Proceedings of 2002 IEEE International Conference on VLSI in Computers and Processors, Sep. (2002) 8-13
  4. Musoll, E., Lang, T., Cortadella, J.: Exploiting the Locality of Memory References to Reduce the Address Bus Energy. Proceeding of 1997 International Symposium on Low Power Electronics and Design, Aug. (1997) 202-207
  5. Kim, H., Park, I. C.: High-Performance and Low-Power Memory-Interface Architecture for Video Processing Applications. IEEE Transactions on Circuits and Systems for Video Technology, Vol. 11, Issue 11, Nov. (2001) 1160-1170 https://doi.org/10.1109/76.964782
  6. Kapoor, B.: Low Power Memory Architectures for Video Applications. Proceedings of the 8th Great Lakes Symposium on VLSI, Feb. (1998) 2-7
  7. Brockmeyer, E., Nachtergaele, L., Catthoor, F.V.M., Bormans, J., De Man, H.J.: Low Power Memory Storage and Transfer Organization for the MPEG-4 Full Pel Motion Estimation on a Multimedia Processor. IEEE Transactions on Multimedia, Vol. 1, Issue 2, June (1999) 202-216 https://doi.org/10.1109/6046.766740
  8. Nachtergaele, L., Catthoor, F., Kapoor, B., Janssens, S., Moolenaar, D.: Low Power Storage Exploration for H.263 Video Decoder. Workshop on VLSI Signal Processing IX, 30 Oct.-1 Nov. (1996) 115-124
  9. Landman, P.: Low-Power Architectural Design Methodologies. PhD thesis, U.C. Berkeley, Aug. (1994)
  10. ISO/IEC 14496-10:2003: Coding of Audiovisual Objects-Part 10: Advanced Video Coding, 2003, also ITU-T Recommendation H.264: Advanced Video Coding for Generic Audiovisual Services
  11. Sato, K.; Yagasaki, Y.: Adaptive MC Interpolation for Memory Access Reduction in JVT Video Coding. Proceedings of Seventh International Symposium on Signal Processing and Its Applications, Vol. 1, July (2003) 77-80
  12. Jiahui Zhu; Ligang Hou; Wuchen Wu: High Performance Synchronous DRAMs Controller in H.264 HDTV Decoder. Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on, Vol. 3, Oct. (2004) 1621- 1624