The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Design of an Automatic Generation System for Cycle-accurate Instruction-set Simulators for DSP Processors

DSP 프로세서용 인스트럭션 셋 시뮬레이터 자동생성기의 설계에 관한 연구

  • 홍성민 (서강대학교 전자공학과 대학원 CAD & ES연구실) ;
  • 박창수 (서강대학교 전자공학과 대학원 CAD & ES연구실) ;
  • 황선영 (서강대학교 전자공학과 대학원 CAD & ES연구실)
  • Published : 2007.09.30
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Abstract

This paper describes the system which automatically generates instruction-set simulators cores using the SMDL. SMDL describes structure and instruction-set information of a target DSP machine. Analyzing behavioral information of each pipeline stage of all instructions on a target ASIPS, the proposed system automatically generates a cycle-accurate instruction set simulator in C++ for a target processor. The proposed system has been tested by generating instruction-set simulators for ARM9E-S, ADSP-TS20x, and TMS320C2x architectures. Experiments were performed by checking the functions of the $4{\times}4$ matrix multiplication, 16-bit IIR filter, 32-bit multiplication, and the FFT using the generated simulators. Experimental results show the functional accuracy of the generated simulators.

본 논문은 SMDL (Sogang Machine Description Language)을 이용한 DSP 프로세서용 인스트럭션 셋 시뮬레이터 자동 생성기 시스템의 설계에 관해 기술한다. SMDL은 DSP 어플리케이션에 최적화된 아키텍처를 포함한 임베디드 코어의 효율적 기술을 위한 머신 기술 언어로서, 구현된 인스트럭션 셋 시뮬레이터 자동 생성 시스템은 타겟 ASIP의 SMDL 기술을 입력으로 하여 인스트럭션들의 파이프라인 스테이지 별 행위 정보를 분석한 후 cycle-accurate 인스트럭션 셋 시뮬레이터를 C++ 파일로 자동 생성한다. 구현된 자동 생성 시스템의 검증을 위해 ARM9E-S, ADSP-TS20x와 TMS320C2x 아키텍처들을 SMDL로 기술하여 시뮬레이터들을 자동 생성하였으며, 생성된 시뮬레이터들을 이용하여 $4{\times}4$ 매트릭스 곱셈, 16비트 IIR 필터, 32비트 곱셈, 그리고 FFT에 연산에 대한 시뮬레이션을 수행하였다. 결과 생성된 시뮬레이터의 정확한 동작을 확인하였다.

Keywords

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