전자공학회논문지SC (Journal of the Institute of Electronics Engineers of Korea SC)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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다수의 병렬 입.출력 환경을 위한 높은 노이즈 마진을 갖는 LVDS I/O 회로

High Noise Margin LVDS I/O Circuits for Highly Parallel I/O Environments

  • 김동규 (삼성전자(주) 메모리사업부) ;
  • 김삼동 (동국대학교 전자공학과) ;
  • 황인석 (동국대학교 전자공학과)
  • 발행 : 2007.01.25
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초록

본 논문에서는 다수의 병렬 입.출력 환경을 위한 높은 노이즈 마진을 갖고 있는 LVDS I/O 회로를 소개한다. 제안된 LVDS I/O회로는 송신단과 수신단으로 구성되어 있으며 송신단 회로는 차동위상 분할기와 공통모드 피드백(common mode feedback)을 가지고 있는 출력단으로 이루어져 있다. 차동위상 분할기는 SSO(simultaneous switching output) 노이즈에 의해 공급전압이 변하더라도 안정된 듀티 싸이클(duty cycle)과 $180^{\circ}$의 위상차를 가진 두 개의 신호를 생성한다. 공통모드 피로백을 가지고 있는 출력단 회로는 공급전압의 변화에 상관없이 일정한 출력전류를 생성하고 공통모드 전압(common mode voltage)을 ${\pm}$0.1V 이내로 유지한다. LVDS 수신단 회로는 VCDA(very wide common mode input range differential amplifier)구조를 사용하여 넓은 공통 입력전압 범위를 확보하고 SSO 노이즈에 의한 공급 전압의 변화에도 안정된 듀티 싸이클(50% ${\pm}$ 3%)을 유지하여 정확한 데이터 복원이 가능하다. 본 논문에서 제안한 LVDS I/O 회로는 0.18um TSMC 라이브러리를 기본으로 하여 설계 되었으며 H-SPICE를 이용하여 시뮬레이션 하였다.

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

키워드

참고문헌

  1. IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), 1596.3 SCI-LVDS Standard, IEEE Std. 1596.3-1996, 1994
  2. R. Senthinathan, J. L. Prinnce, 'Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise,' IEEE JSSC, vol. 28, no. 12, pp. 1383-1388, Dec. 1993 https://doi.org/10.1109/4.262016
  3. Huainan Ma, Sher Jiun Fang, Fujiang Lin, Hiroshi Nakamura, 'Novel Active Differential Phase Splitters in RFIC for Wireless Applications,' IEEE Trans. Microwave Theory and Techniques, vol. 46, no. 12, pp. 2597-2603, Dec. 1998 https://doi.org/10.1109/22.739252
  4. Uwe Vogel, Marcel Steinert, Rainer Kokozinski 'LVDS I/O Cells with Rail-to-Rail Receiver Input for SONET/SDH at 1.25Gb/s,' ESSCIRC, pp. 460-463, September 2000
  5. Bazes, M., 'Two Novel Fully Complementary Self Biased CMOS Differential Amplifiers,' IEEE Journal of Solids-States Circuits, vol. 26, no. 2, pp. 165-168, Feb. 1991 https://doi.org/10.1109/4.68134
  6. Andrea Boni, Andrea Pierazzi, Davide Vecchi 'LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35-um CMOS,' IEEE JSSC, vol. 36, no. 4, pp. 706-711, April, 2001 https://doi.org/10.1109/4.913751