References
- Said F. Al-sarawi, Derek Abbott and Paul D. Franzon, 'A Review of 3-D Packaging Technology', IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY PART B, 21-1 (1998. 2)
- C.S.Premachandran, Ranganathan Nagarajan, Chen Yu, Bang Xiolin and Chong Ser Choong, 'A Novel Electrically Conductive Wafer Through Hole Filled Vias InterconnectFor 3D MEMS Packaging', 2003 Electronic Components and Technology Conference
- Ik-Bu Sohn, Man-Seop Lee, and Jeong-Yong Chung, 'Fabrication of Optical Splitter and Passive Alignment Technique With a Femtosecond Laser', IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 17-11 (2005. 11)
- R.Bosch Gmbh, US Patent 4855017 and 4784720, (1994)
- Manabu Tomisaka, Masataka Hoshino, Hitoshi Yonemura, Kenji Takahashi, 'Copper Electroplating Study for Through Silicon Chip Electrode of Threedimensional Chip Stacking', DENSO TECHNONOGY REVIEW, 6-2 (2001)
- A.A.Ayon et al., 'Characterization of a time multiplexed inductively coupled plasma etcher', J. Electrochem. Soc., 146 (1999), 339-349 https://doi.org/10.1149/1.1391611
- K.S.Chen et al., 'Effect of process parameters on the surface morphology and mechanical performance of silicon structures after deep reactive ion etching (DRIE)', J. of microelectromechanical Sys., 11-3 (2002), 264-274
- K.S.Chen et al., “Tailoring and testing the fracture strength of silicon at the mesoscale”, J. of Amer. Cera. Soc., 83 (2000), 1476-1484 https://doi.org/10.1111/j.1151-2916.2000.tb01413.x
- Hara K., Kurashima Y. Hashimoto N., Matsui K., Matsuo Y., Miyazawa I., Kobayashi T., Yokoyama Y. and Fukazawa M., 'Optimization for Chip Stack in 3-D Packaging', IEEE transaction on advannced packaging, 28-3 (2005. 8)