Journal of information and communication convergence engineering

  • 제4권2호
  • /
  • Pages.84-87
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  • 2006
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  • 2234-8255(pISSN)
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  • 2234-8883(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
권호 표지

Spatial Distribution of Localized Charge Carriers in SONOS Memory Cells

  • Kim Byung-Cheul (Department of Electronic Engineering, Jinju National University)
  • 발행 : 2006.06.01
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초록

Lateral distributions of locally injected electrons and holes in an oxide-nitride-oxide (ONO) dielectric stack of two different silicon-oxide-nitride-oxide-silicon (SONOS) memory cells are evaluated by single-junction charge pumping technique. Spatial distribution of electrons injected by channel hot electron (CHE) for programming is limited to length of the ONO region in a locally ONO stacked cell, while is spread widely along with channel in a fully ONO stacked cell. Hot-holes generated by band-to-band tunneling for erasing are trapped into the oxide as well as the ONO stack in the locally ONO stacked cell.

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참고문헌

  1. M. H. White, D. A. Adams, J. Bu, 'On the go with SONOS,' IEEE Circuits and Devices Magazine, vol. 16, pp. 22-31, 2000 https://doi.org/10.1109/101.857747
  2. J. Bu, M.H. White, 'Electrical characterization of ONO triple dielectric in SONOS nonvolatile memory devices,' Solid-State Electron, vol. 45, pp. 47-51. 2001 https://doi.org/10.1016/S0038-1101(00)00194-5
  3. Stephen J. Wrazien, Yijie Zhao, Joel D. Krayer, Marvin H. White, 'Characterization of SONOS oxynitride nonvolatile semiconductor memory devices,' Solid-State Electron, vol. 47, pp. 885-891, 2003 https://doi.org/10.1016/S0038-1101(02)00448-3
  4. Rob van Schaijk, Michiel van Duuren, Wan Yuet Mei, Kees van der Jeugd, Aude Rothschild, Marc Demand, 'Oxide-nitride-oxide layer optimisation for reliable embedded SONOS memories,' Microelectronic Engineering, vol. 72, pp. 395-398, 2004 https://doi.org/10.1016/j.mee.2004.01.021
  5. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, 'NROM: A Novel Localized Trapping, 2-Bit Nonvolatile memory Cell,' IEEE Electron Device Lett., vol. 21, pp. 543-545, 2000 https://doi.org/10.1109/55.877205
  6. C. C. Yeh, W. J. Tsai, M. I. Liu, T. C. Lu, S. K. Cho, C. J. Lin, Tahui Wang, Sam Pan, and Chih-Yuan Lu, 'PHINES : a novel low power program/erase, small pitch, 2-bit per cell flash memory,' IEDM Tech. Digest, pp. 931-934, 2002
  7. H. Haddara, S. Cristoloveanu, 'Two-dimensional modeling of locally damaged short-channel MOSFET's operating in the linear region,' IEEE Trans Electron Dev., vol. 34, pp. 378-385, 1987 https://doi.org/10.1109/T-ED.1987.22933
  8. E. Lusky, Y. Shacham-Diamand, I. Bloom, B. Eitan, 'Characterization of channel hot electron injection by the subthreshold slope of $NROM^{TM}$ device,' IEEE Electron Device Lett., vol. 22, pp. 556-558, 2001 https://doi.org/10.1109/55.962662
  9. L. Larcher, G. Verzellesi, P. Pavan, E. Lusky, I. Bloom, B. Eitan, 'Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells,' IEEE Trans Electron Dev., vol. 49, pp. 1939-1946,2002 https://doi.org/10.1109/TED.2002.804726
  10. A. Shappir, E. Lusky, Y. Shacham-Diamand, I. Bloom, S. Eitan, 'Subthreshold slope degradation model for localized charge-trapping based non-volatile memory devices,' Solid-State Electron, vol. 47, pp. 937-941, 2003 https://doi.org/10.1016/S0038-1101(02)00454-9