JSTS:Journal of Semiconductor Technology and Science

  • 제6권4호
  • /
  • Pages.246-251
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  • 2006
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

An Implementation Method of Cycle Accurate Simulator for the Design of a Pipelined DSP

  • Park, Hyeong-Bae (Dept. of Electronics Engineering Pusan National Univ.) ;
  • Park, Ju-Sung (Dept. of Electronics Engineering Pusan National Univ.) ;
  • Kim, Tae-Hoon (Dept. of Electronics Engineering Pusan National Univ.) ;
  • Chi, Hua-Jun (Dept. of Electronics Engineering Pusan National Univ.)
  • 발행 : 2006.12.31
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초록

In this paper, we introduce an implementation method of the CBS (Cycle Base Simulator), which describes the operation of a DSP (Digital Signal Processor) at a pipeline cycle level. The CBS is coded with C++, and is verified by comparing the results from the CBS and HDL simulation of the DSP with the various test vectors and application programs. The CBS shows the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The developed CBS can be used in evaluating the performance of the target DSP before the RTL(Register Transfer Level) coding as well as a reference for the RTL level design.

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참고문헌

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