JSTS:Journal of Semiconductor Technology and Science

  • 제6권4호
  • /
  • Pages.240-245
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  • 2006
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

A Bit-level ACSU of High Speed Viterbi Decoder

  • Kim, Min-Woo (Electronic & Electrical Eng. Dept. Sungkyunkwan University) ;
  • Cho, Jun-Dong (Electronic & Electrical Eng. Dept. Sungkyunkwan University)
  • 발행 : 2006.12.31
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초록

Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.

키워드

참고문헌

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