UWB 시스템을 위한 1.8V 8-bit 500MSPS 저 전력 CMOS D/A 변환기의 설계

Design of an 1.8V 8-bit 500MSPS Low-Power CMOS D/A Converter for UWB System

  • 발행 : 2006.12.25

초록

본 논문에서는 UWB(Ultra Wide Band)통신시스템을 위한 1.8V 8-bit 500MSPS의 D/A 변환기를 제안한다. 전체적인 D/A 변환기의 구조는 높은 선형성과 낮은 글리치 특성을 갖는 상위 6-MSB(Most Significant Bit) 전류원 매트릭스(Current Cell Matrix)와 하위 2-LSB(Least Significant Bit) 전류원 매트릭스로 구성된 2단 매트릭스 구조로 설계하였다. 또한 동일한 지연시간을 갖는 Thermometer Decoder와 고속 동작에서 전력을 최소화하기 위한 저 전력 스위칭 디코더(Current Switching Decoder Cell)를 제안함으로서 D/A 변환기의 고속 동작에서 성능을 향상시켰다 설계된 DAC는 1.8V의 공급전압을 가지는 TSMC $0.18{\mu}m$ 1-poly 6-metal N-well CMOS 공정으로 제작되었으며, 제작된 D/A 변환기의 측정결과, 매우 우수한 동적성능을 확인하였다. 500MHz 샘플링 클럭 주파수와 50MHz의 출력신호에서 SFDR은 약 49dB, INL과 DNL은 각각 0.9LSB, 0.3LSB 이하로 나타났으며, 이 때의 전력소비는 약 20mW로 기존의 8-bit D/A변환기에 비해 매우 낮음을 확인 할 수 있었다 D/A 변환기의 유효 칩 면적은 $0.63mm^2(900um{\times}700um)$이다.

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

키워드

참고문헌

  1. David A. Johns and Ken Martin, 'Analog Integrated Circuit Design', John Wiley & Sons Inc., 1997, pp. 463-486
  2. Rudy van de Plassche, 'CMOS Integrated Analog to Digital and Digital to Analog Converter', Kluer Academic Publisher, 2003, pp. 205-235
  3. Wang, S. and Omair Alunad, M., 'A switched-current ratio-independent algorithmic D/A converter' Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on Volume 2, 30 May-2 June 1999 Page(s):101 - 104 vol.2 https://doi.org/10.1109/ISCAS.1999.780629
  4. Yijun Zhou and Iiren Yuan, 'An 8-bit 100-MHz CMOS linear interpolation DAC' Solid-State Circuits, IEEE Journal of Solid State, Volume 38, Issue 10, Oct. 2003 Page(s):1758 - 1761 https://doi.org/10.1109/JSSC.2003.817593
  5. Huei-Chi Wang, Hong-Sing Kao, Tai-Cheng Lee, M. 'An 8-bit 2-V 2-mW 0.25-mm/sup 2/CMOS DAC' Advanced System Integrated Circuits 2004: Proceedings of 2004 IEEE Asia-Pacific Conference on 4-5 Aug. 2004 Page(s):102 - 105 https://doi.org/10.1109/APASIC.2004.1349418
  6. J. H. Kim and K. S. Yoon, 'An 8-Bit CMOS 3.3V 65MHz Digital to Analog Converter with a Symmetric Two-Stage Current Cell Matrix Architecture' IEEE Trans. Circuits Systs, II, vol. 45, no. 12, pp. 1605-1609, Dec. 1998 https://doi.org/10.1109/82.746683
  7. Sanghoon Hwang and Minkyu Song, 'A 10-b 500 MSPS current-steering CMOS D/A converter with a self-calibrated current biasing technique' Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on 13-15 Dec. 2004 Page(s):254 - 257 https://doi.org/10.1109/ICECS.2004.1399666
  8. Weibiao Zhang and Hassoun M., 'A redundant-cell-relay continuous self-calibration method for current-steering DACs' Solid-State Circuits conference, ESSCIRC 2001. 18-20 Sept. 2001 Page(s):349-352
  9. Younhua Cong: Geiger,R.L, 'A 1.5V 12-bit 100-MS/s self-calibrated DAC' Solid-State Circuits, IEEE Jounal of, Volume 38, Issue 12, Dec 2003 Page(s):2051-2060 https://doi.org/10.1109/JSSC.2003.819163
  10. Baschirotto. A, Ghittori. N, Malcovati. P, Vigan. A, 'Design trade-offs for a 10 bit, 80MHz current steering digital-to-analog converter' The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004, 20-23 June 2004, Page(s):249-252 https://doi.org/10.1109/NEWCAS.2004.1359078
  11. 이승훈, 김범섭, 송민규, 최중호 공저, 'CMOS 아날로그 / 혼성모드 집적시스템 설계(상)', 시그마프레스, 1999, pp. 98-106
  12. 이승훈, 김범섭, 송민규, 최중호 공저, 'CMOS 아날로그 / 혼성모드 집적시스템 설계(하)', 시그마프레스, 1999, pp. 63-98