References
- E. A. Lee and D.G. Messerschmitt, 'Synchronous data flow, 'Proceedings of the IEEE, vol.75, no.9, pp. 1235-1245, September 1987 https://doi.org/10.1109/PROC.1987.13876
- S.M. Heemstra de Groot, S.H. Gerez, and O.E. Herrmann,'Range-chart-guided iterative data-flow- graph scheduling,' IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 39, pp. 35-{364, May 1992 https://doi.org/10.1109/81.139286
- K. K. Parhi and D.G. Messerschmitt, 'Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding, 'IEEE Transactions on Computers, vol. 40, no. 2, pp. 178-195, February 1991. PROGRESS 2000 Workshop on Embedded Systems, Utrecht, The Netherlands, October 2000.8 https://doi.org/10.1109/12.73588
- S. H. Gerez, S.M. Heemstra de Groot, E.R. Bonsma, and M.J.M. Heijligers, 'Overlapped scheduling techniques for high-level synthesis and multiprocessor realizations of DSP algorithms,' in Advanced Techniques for Embedded System Design and Test, J.C. Lopez, R. Hermida, and W. Geisselhardt, Eds., pp. 125-150
- G. Goossens, J. Rabaey, J. Vandewalle, and H. De Man, 'An efficient microcode compiler for application specific DSP processors,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 9, pp. 925-937, September 1990 https://doi.org/10.1109/43.59069
- T.F. Lee, A.C.H. Wu, Y.L. Lin, and D.D. Gajski, 'A transformation-based method for loop folding,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 4,pp. 439-450, April 1994 https://doi.org/10.1109/43.275354
- V. K. Madisetti, VLSI Digital Signal Processors, An Introduction to Rapid Prototyping and Design Synthesis, IEEE Press and Butterworth Heinemann, Boston, 1995
- J. Sanchez and H. Barral, 'Multiprocessor implementation models for adaptive algorithms,' IEEE Transactions on Signal Processing, vol. 44, no. 9, pp. 2319-2331, September 1996 https://doi.org/10.1109/78.536687
- S. Sriram and S.S. Bhattacharyya, Embedded Multiprocessors, Scheduling and Synchronization, Marcel Dekker, New York, 2000
- D.C. Chen and J.M. Rabaey, 'A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths,' IEEE Journal of Solid-State Circuits, vol. 27, no.12, pp. 1895-1904, December 1992 https://doi.org/10.1109/4.173120