JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Dual Edge-Triggered NAND-Keeper Flip-Flop for High-Performance VLSI

  • Kim, Jae-Il (Department of Electronics Telecommunication and Computer Engineering, Hankuk Aviation University) ;
  • Kong, Bai-Sun (epartment of Electronics Telecommunication and Computer Engineering, Hankuk Aviation University)
  • Published : 2003.06.01
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Abstract

This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-to-output latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows negative setup time to provide useful attribute of soft clock edge by incorporating the pulse-triggered operation. The proposed flip-flop was designed using a $0.35{\;}\mutextrm{m}$ CMOS technology. The simulation results indicate that, for the typical input switching activity of 0.3, DETNKFF reduces power consumption by as much as 21 %. Latency is also improved by about 6 % as compared to the conventional flip-flop. The improvement of power-delay product is also as much as 25 %.

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References

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