정보와 통신 (Information and Communications Magazine)

한국통신학회 (The Korean Institute of Commucations and Information Sciences)
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SDR을 위한 기저대역 신호처리 소자 기술

  • 발행 : 2002.11.01
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참고문헌

  1. SDR Forum [Online]. Available: http: //www .sdrforum.org
  2. Semiconductor Industry Association [Online].Available: http://www.semichips.org
  3. L. Pucker, 'Wireless infrastructure: paving paths to software radio design [Online].' Available: http://www.commsdesign.com/story/ OEG20010521S0118
  4. H. Zhang, V. Prabhu, V. George, M. Wan, M. Benes, A. Abnous, and J. M. Rabaey, 'A 1-V heterogeneous reconfigurable DSP IC for wireless baseband,' IEEE Journal of Solid-State Circuits, vol. 35, pp.1697-1704, Nov. 2000 https://doi.org/10.1109/4.881217
  5. H. Meyr, 'Why we need all these MIPS in future wireless communication systems and how to design algorithms and architecture for these systems,' in Proc. IEEE Workshop on Signal Processing Systems, 2001, pp. 2
  6. K. Bondalapati, and V. K. Prasanna, 'Reconfigurable computing systems,'Proceedings of the IEEE, vol. 90, pp. 1201-1217, July 2002
  7. I. Kramberger, 'DSP acceleration using a reconfigurable FPGA,' in Proc. IEEE International Symposium on Industrial Electronics, vol. 3, 1999. pp. 1522-1525
  8. J. R. Hauser, and J. Wawrzynek, 'Garp: a MIPS processor with a reconfigurable coprocessor,' in Proc. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1997, pp. 12-21
  9. G. Sassatelli, L. Torres, P. Benoit, T. Gil, C. Diou, G. Cambon, and J. Galy, 'Highly scalable dynamically reconfigurable systolic ring architecture for DSP applications,' in Proc. Design, Automation and Test in Europe Conference and Exhibition. 2002, pp. 553-558
  10. G. W. Donohoe, and P. S. Yeh, 'Low power reconfigurable processor,' in Proc. IEEE Aerospace Conference. vol. 4, 2002, pp. 1969-1973
  11. L. I. Chen, W. L. Liu, O. T. Chen and R. L. Ma, 'A reconfigurable digital signal processor architecture for high efficiency mpeg 4 video encoding,' in Proc. IEEE International Conference on Multimedia and Expo. vol. 2, 2002, pp. 165-168
  12. Xilinx Platform FPGAs [Online]. Available: http://www.xilinx.com
  13. B. Salefski, and L. Caglar, 'Re configurable computing in wireless,' in Proc. Design Automation Conference 2001, pp. 178-183
  14. Chameleon Systems [Online]. Available: http://www.chameleonsystems.com
  15. Electronic Engineering Times, Feb. 1 2001
  16. Jung Hoo Lee, Jae Sung Lee, Myung H. Sunwoo, and Kyung Ho Kim, 'Design of new DSP instructions and their hardware architecture for the Viterbi decoding algorithm,' in Proc.International Symposium on Circuits and Systems (ISCAS2002), Phoenix, Arizona, USA, May 2002, pp. 561-564
  17. Jae S. Lee and Myung H. Sunwoo, 'Design of DSP instructions and their hardware architecture for a REED SOLOMON codec,' in Proc. Signal Processing Systems (SIPS2002). San Diego, California, USA, Oct. 2002
  18. Y. Bajot, and H. Mehrez, 'Cus tomizable D8P architecture for ASIP core design,' in Proc. IEEE International Symposium on Circuits and Systems, vol. 4, 2001, pp. 302-305
  19. Jae S. Lee, Young S. Jeon. and Myung H. Sunwoo, 'Design of new DSP instructions and their hardware architecture for high speed FFT,' in Proc. Signal Processing Systems(SIPS 2001), Belgium, Sep. 2001, pp. 80-90
  20. P. C. Tseng, C. K. Chen, and L. G. Chen, 'CDSP: an application specific digital signal processor for third generation wireless communications, IEEE Transactions on Consumer EIectronics, vol. 47, pp. 672-677, Aug. 2001 https://doi.org/10.1109/30.964162
  21. SandbridgeTechnologies Inc [Online]. Available: http://www.sandbridgetech.com
  22. Motorola Inc [Online]. Available: http://e-www.motorola.com
  23. J. Glossner, J. Moreno, M. Moudgill, J. Derby, E. Hokenek, D. Meltzer, U Shvadron, and M. Ware, 'Trends in compilable DSP architecture,' in Proc. IEEE Workshop Signal Processing Systems: Design and Implemenatation, Oct. 2000, pp. 181-199
  24. T. Nishikawa. M. Takahashi, M. Hamada, T. Takayanagi, H. Arakida N. Machida, H. Yamamoto, T Fujiyoshi, Y. Maisumoto, O. Yamagishi, T. Samata, A. Asano, T. Terazawa, K. Ohmori, J. Shirakura, Y. Watanabe, H. Nakamura. S. Minami, T. Kuroda, and T. Furuyama, 'A 60MHz 240mW MPEG-4 video-phone LSI with 16Mb embedded DRAM,' in Proc. IEEE Int Solid-State Circuits Conference. Feb. 2000, pp. 230-231
  25. S. Kurohmaru, M. Matsuo,H. Nakajima, Y. Kohashi, T. Yonezawa T. Moriiwa, M. Ohashi, M. Toujima, T. Nakamura, M. Hamada, T. Hashimoto, H. Fujimoto, Y. lizuka, J. Michiyama. and H. Komori, 'A MPEG4 programmable codec DSP with an embedded pre/Post-processing engine,' in Proc. IEEE Custom Integrated Circuits Conference. May 1999, pp. 69-72
  26. StarCore LLC [Online]. Available: http://www.starcore-dsp.com
  27. Texas Instruments [Online]. Available: http://www.ti.com
  28. J. Williams, B. Ackland, and N. Heintze, 'Communication mechanisms for parallel DSP systems on a chip,' in Proc. Design, Automation and Test in Europe Conference and Exhibition, 2002, pp. 420-422
  29. S. K. Tewksbury, V. Gandakota, K. Devabattini, and P. Adabala, 'Integrated memory/network architectures for cluster organized, parallel DSP architectures,' in Proc. IEEE Symposium on IC/Package Design Integration. 1998, pp. 21-26
  30. B. Ackland, A. Anesko. D. Brinthaupt. S. J. Daubert. A. Kalavade, J. Knobloch, E. Micca, Moturi, C. J. Nicol, J. H. O'Neill, J. Othmer, E. Sackinger, K. J. Singh, J.Sweet, C. J. Terman. and J.Williams, 'A single chip, 1.6-billion 16-b MAC/s multiprocessor DSP, IEEE Journal of Solid State Circuits,vol. 35, pp. 412-424, March 2000 https://doi.org/10.1109/4.826824
  31. O. Paker, J. Sparso, N. Haandbaek, M. Isager, and L. S. Nielsen, 'A heterogeneous multiprocessor architecture for low power audio signal processing applications,' in Proc. IEEE Computer Society Workshop on VLSI, 2001, pp. 47-53