Journal of electromagnetic engineering and science

The Korean Institute of Electromagnetic Engineering and Science (한국전자파학회)
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Multilayer Power Delivery Network Design for Reduction of EMI and SSN in High-Speed Microprocessor System

  • Park, Seong-Geun (Dept. of Electrical and Electronic Eng., Yonsei Univ.) ;
  • Kim, Ji-Seong (R&D Group, Computer Division, Samsung Electronics) ;
  • Yook, Jong-Gwan (Dept. of Electrical and Electronic Eng., Yonsei Univ.) ;
  • Park, Han-Kyu (Dept. of Electrical and Electronic Eng., Yonsei Univ.)
  • Published : 2002.11.01
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Abstract

In this paper, a pre-layout design approach for high-speed microprocessor is proposed. For multilayer PCB stark up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system. The system model includes VRM, decoupling capacitors, multiple power and ground planes for core voltage, vias, as well as microprocessor. Finally, the simulation results are verified by measurements data.

Keywords

References

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