Transactions on Electrical and Electronic Materials

  • 제3권1호
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  • Pages.4-8
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  • 2002
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  • 1229-7607(pISSN)
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  • 2092-7592(eISSN)
한국전기전자재료학회 (The Korean Institute of Electrical and Electronic Material Engineers)
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Fabrication of Field-Emitter Arrays using the Mold Method for FED Applications

  • Cho, Kyung-Jea (Department of Physics, Kyungpook National University) ;
  • Ryu, Jeong-Tak (Department of Computer and Communication Engineering, Taegu University) ;
  • Kim, Yeon-Bo (Department of Computer and Communication Engineering, Taegu University) ;
  • Lee, Sang-Yun (Department of Physics, Kyungpook National University)
  • 발행 : 2002.03.01
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초록

The typical mold method for FED (field emission display) fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by LPCVD (low pressure chemical vapor deposition), and then BPSG (Boro phosphor silicate glass) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed.

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참고문헌

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