A Minimization Technique for BDD based on Microcanonical Optimization

Microcanonical Optimization을 이용한 BDD의 최소화 기법

  • 이민나 (한국외국어대학교 대학원 컴퓨터공학과) ;
  • 조상영 (한국외국어대학교 컴퓨터공학과)
  • Published : 2001.03.01

Abstract

Using BDD, we can represent Boolean functions uniquely and compactly, Hence, BDD have become widely used for CAD applications, such as logic synthesis, formal verification, and etc. The size of the BDD representation for a function is very sensitive to the choice of orderings on the input variables. Therefore, it is very important to find a good variable ordering which minimize the size of the BDD. Since finding an optimal ordering is NP-complete, several heuristic algorithms have been proposed to find good variable orderings. In this paper, we propose a variable ordering algorithm based on the $\mu$O(microcanonical optimization). $\mu$O consists of two distinct procedures that are alternately applied : Initialization and Sampling. The initialization phase is to executes a fast local search, the sampling phase leaves the local optimum obtained in the previous initialization while remaining close to that area of search space. The proposed algorithm has been experimented on well known benchmark circuits and shows superior performance compared to a algorithm based on simulated annealing.

Keywords

References

  1. S. B. Akers, 'Binary Decision Diagrams,' IEEE Transaction on Computers, Vol.C-27, No.6, pp.509-516, August 1978 https://doi.org/10.1109/TC.1978.1675141
  2. Randal E. Bryant 'Symbolic Manipulation of Boolean Functions Using a Graphical Representation,' 22nd Design Automation Conference, pp.688-694, une 1985 https://doi.org/10.1145/317825.317964
  3. Randall E. Bryant, 'Graph-Based Algorithms for Boolean Function Manipulation,' IEEE Transaction on Computers, Vol.C-35, pp.667-691, August 1986 https://doi.org/10.1109/TC.1986.1676819
  4. Randal E. Bryant, 'Symbolic Boolean Manipulation with Ordered Binary Decision Diagrams,' ACM Computing Surveys, Vol.24, No.3, September 1992 https://doi.org/10.1145/136035.136043
  5. Randal E. Bryant, 'Binary Decision Diagrams and Beyond: Enabling Technologies for Formal Verification,' International Conference on Computer Aided Design, pp.236-243, November 1995 https://doi.org/10.1109/ICCAD.1995.480018
  6. Saeyang Yang, 'Logic Synthesis and Optimization Benchmarks User Guide Version 3.0,' Distributed as part of the IWLS91 benchmark distribution, January 15, 1991
  7. Richard Rudell, 'Dynamic Variable Ordering of Ordered Binary Decision Diagrams,' International Conference on Computer-Aided Design, pp.43-47, November 1993 https://doi.org/10.1109/ICCAD.1993.580029
  8. D. Moller, P. Molitor, R. Orechsler, 'Symmetry based variable ordering for Obdds,' IFIP Workshop on Logic and Architecture Synthesis, Grenoble, December, 1994
  9. S. Panda, F. Somenzi, 'Who are the variables in your neighborhood,' In Proceedings of the International Conference on Computer-Aided Design, pp.74-77, San Jose,CA, November 1995 https://doi.org/10.1109/ICCAD.1995.479994
  10. B. Bolling, M. Lobbing, I. Wegener, 'Simulated Annealing to improve variable orderings for OBDDs,' International workshop on Logic Synthesis, pp.5b:5.1-5.10, 1995
  11. Rolf Drechsler, Bernd Beckern, Nicole Gockel, 'A Genetic Algorithm for Variable Ordering of OBDDs,' International workshop on Logic Synthesis, pp.5C:5.55-5.64, 1995
  12. Fabio Somenzi, 'CUDD: CU Decision Diagram Package Release 2.3.0.,' University of Colorado, April 12, 1997
  13. Rolf Drechsler, Nicole Gockel, 'Simulation Based Minimization of large OBDDs,' Preprint at the Institute of Computer Science, Albert-Ludwigs-University Freiburg im Breisgau, germany, January 1997
  14. Rolf Drechsler, Nicole Gockel, 'Minimization of BDDs by Evolutionary Algorithms,' International Workshop on Logic Synthesis (IWLS'97), Lake Tahoe, 1997
  15. Rolf Drechsler, Bernd Becker, 'Binary Decision Diagrams: Theory and Implementation,' Kluwer Academic Publishers, 1998
  16. S. J. Fredman, K. J. Supowit, 'Finding the Optimal Variable Ordering for Binary Decision Diagrams,' IEEE Transaction on Computers, Vol.C-39, No.5, pp.710-713, May 1990 https://doi.org/10.1109/12.53586
  17. H. Fujii, G. Otomo, G. Hori, 'Interleaving Based Variable Ordering Methods for Ordered Binary Decision Diagrams: International Conference on Computer-Aided Design,' pp.622-627, Nov. 1993 https://doi.org/10.1109/ICCAD.1993.580028
  18. Alan J.Hu, 'Fornmal Hardware Verification with BDDs: introduction,' IEEE pacific Rim Conference on Communications, Computers and Signal Processing(PACRIM'97), 1997 https://doi.org/10.1109/PACRIM.1997.620351
  19. Christoph Scholl, Rolf Drechsler, Bernd Becker, 'Functional Simulation using Binary Decision Diagrams,' ACM/IEEE International Conference on Computer Aided Design(ICCAD'97), pp.8-12, San Joes, 1997 https://doi.org/10.1109/ICCAD.1997.643253
  20. M. Creutz, 'Microcanonical Monte Carlo simulation,' Phys, Rev, Lett, Vol.50, pp.1411-1413, 1983 https://doi.org/10.1103/PhysRevLett.50.1411
  21. Alexandre Linhares, Horacio H. Yanasse, Jose R.A.Torreao, 'Linear Gate Assignment: A Fast Statistical Mechanics Approach,' IEEE Transaction on Computer-Aided Design of Intergrated circuits and system, Vol.18, No.12, December 1999 https://doi.org/10.1109/43.811324
  22. S. C S. Porto, A. M. Barrose, J. R. A.Torreao, 'A Parallel Microcanonical Optimization Algorithm for the Task scheduling Problem,' Technical Report, Applied Computing & Automation Universidado Fluminense, September 1999
  23. A. Linhares, J. A. Torreao, 'Microcanonical optimization applied to the traveling salesman problem,' Int. J. Modern Phys. C, Vol.9, pp.133-146, 1998 https://doi.org/10.1142/S012918319800011X