Journal of Institute of Control, Robotics and Systems (제어로봇시스템학회논문지)

Institute of Control, Robotics and Systems (제어로봇시스템학회)
권호 표지

Petri nets modeling and dynamic scheduling for the back-end line in semiconductor manufacturing

반도체 후공정 라인의 페트리 네트 모델링과 동적 스케쥴링

  • Published : 1999.08.01
Download PDF
⟨ Previous Next ⟩

Abstract

An effective method of system modeling and dynamic scheduling for the back-end line of semiconductor manufacturing is proposed. The virtual factory, describing semiconductor manufacturing line, is designed in detail, and then a Petri net model simulator is developed for operation and control of the modular cells of the virtual factory. The petri net model is a colored timed Petri nets (CTPNs). The simulator will be utilized to analyze and evaluate various dynamic status and operatons of manufacturing environments. The dynamic schedulaer has a hierarchical structure with the higher for planning level and the lower for dynamic scheduling level. The genetic algorithm is applied to extract optimal conditions of the scheduling algorithm. The proposed dynamic scheduling is able to realize the semiconductor manufacturing environments for the diversity of products, the variety of orders by many customers, the flexibility of order change by changing market conditions, the complexity of manufacturing processes, and the uncertainty of manufacturing resources. The proposed method of dynamic scheduling is more effective and useful in dealing with such recent pressing requirements including on-time delivery, quick response, and flexibility.

Keywords

References

  1. IEEE Trans Semiconductor Manufacturing v.1 no.3 Scheduling Semiconductor Wafer Fabrication L. M. Wein
  2. Proc. Int'l Conf. Robotics and Automation v.3 Daily scheduling for R&D semiconductor fabrication D.-Yi. Liao;S.-C. Chang;S.-R. Yen;Cheng-Chung Chien
  3. IEEE Trans. Semiconductor Manu- facturing v.9 no.2 A Production Planning Methodology for Semiconductor Manufacturing Based on Iterative Simulation and Linear Progarmming Calculations Y.-F. Hung;R. C. Leachman
  4. Operation Research v.36 no.3 Development and implementation of a scheduling system for a wafer fabrication facility G. R. Bitran;Devanath Tirupati
  5. IEEE Trans. Semiconductor Manufacturing v.2 no.4 A robust production control policy for VLSI Wafer Fabrication S. X. C. Lou;P. W. Kager
  6. Semiconductor Manufacturing v.5 no.4 Efficient algorithms for sche Trans C.-Y. Lee;R. Uzsoy;L. A. Martin-Vega
  7. IEEE Trans. Semiconductor Manufacturing v.5 no.4 Control of batch processing systems in semiconductor wafer fabrication facilities H. Gurnani;R. Anupindi;R. Akella
  8. IEEE Trans. Semiconductor Manufacturing v.4 no.4 Production scheduling algorithms for a semiconductor test facility R. Uzsoy;L. A. Martin-Vega;C.-Y. Lee;P. A. Leonard
  9. IEEE Trans. Semiconductor Manufacturing v.11 no.3 Scheduling of semiconductor test facility via petri nets and hybrid heuristic search H. H. Xiong;M. Zhou
  10. IEEE Trans. Components, Packaging, and Manufacturing Technology v.20 no.4 A scheduling system for IC packaging industry using STEP enabling technology T.-H. Liu;A. J. C. Trappey;F.-W. Chan
  11. Genetic Algorithms in Search, Optimization, & Machine Learning D. E. Goldberg
  12. IEEE Trans. Systems, Man, and Cybernetics v.1 Optimization of control parameters for genetic algorithms J. J. Grefenstette
  13. IIE Transactions v.24 no.2 Intelligent scheduling with machine learning capabilities : the induction of scheduling knowledge M. J. Shaw;S. Park;N. Raman
  14. Int'l Journal of Production Research v.30 no.2 Dynamic scheduling system utilizing machine learning as a knowledge acquisition tool S. Nakasuka;T. Yoshida
  15. IEEE Trans. Components, Packaging, and Manufacturing Technology v.20 no.4 A dispatching scheme involving move control and weighted due date for wafer foundries C.-E. Lee;C.-W. Chen